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Author SHA1 Message Date
Tim Northover c94d70336b GlobalISel: tidy up def/use test. NFC. 
llvm-svn: 293545
 2017-01-30 20:52:37 +00:00
Matt Arsenault 1f2ca66317 LSR: Don't drop address space when type doesn't match 
For targets with different addressing modes in each address space,
if this is dropped querying isLegalAddressingMode later with this
will give a nonsense result, breaking the isLegalUse assertions.

This is a candidate for the 4.0 release branch.

llvm-svn: 293542
 2017-01-30 19:50:17 +00:00
Tim Northover 79f43f195c GlobalISel: translate memset & memmove. 
llvm-svn: 293541
 2017-01-30 19:33:07 +00:00
Matt Arsenault af635240d5 AMDGPU: Undo sub x, c -> add x, -c canonicalization 
This is worse if the original constant is an inline immediate.

This should also be done for 64-bit adds, but requires fixing
operand folding bugs first.

llvm-svn: 293540
 2017-01-30 19:30:24 +00:00
Krzysztof Parzyszek 3695d06a10 [RDF] Add support for regmasks 
llvm-svn: 293538
 2017-01-30 19:16:30 +00:00
Tim Northover 480609d0f3 GlobalISel: permit unused vregs without a register-class after ISel. 
This can happen if earlier combining has removed all uses of some VReg, which
is fine and shouldn't flag an error.

llvm-svn: 293537
 2017-01-30 19:12:50 +00:00
Benjamin Kramer a9df941403 Fix the GCC build. 
This is fairly ugly, but apparently GCC still doesn't understand C++11.

llvm-svn: 293535
 2017-01-30 19:05:09 +00:00
Simon Pilgrim ffe2535cf6 Use SelectionDAG::getBuildVector helper function where possible. NFCI. 
llvm-svn: 293532
 2017-01-30 18:53:45 +00:00
Benjamin Kramer a846e0b082 [MC] Remove global constructors from MCSectionMachO.cpp. 
llvm-svn: 293526
 2017-01-30 18:46:26 +00:00
Matt Arsenault 0c3293844b AMDGPU: Run AMDGPUCodeGenPrepare after inlining 
With leaf functions, this makes nonsensical decisions
based on the uniformity of the arguments.

llvm-svn: 293525
 2017-01-30 18:40:29 +00:00
Sanjay Patel 373db5ba6c [InstCombine] enable (X >>?exact C1) << C2 --> X >>?exact (C1-C2) for vectors with splat constants 
llvm-svn: 293524
 2017-01-30 18:40:23 +00:00
Justin Bogner 8f520a73b2 SDAG: Update ChainNodesMatched during UpdateChains if a node is replaced 
Previously, we would hit UB (or the ISD::DELETED_NODE assert) if we
happened to replace a node during UpdateChains, because it would be
left in the list we were iterating over. This nulls out the pointer
when that happens so that we can avoid the issue.

Fixes llvm.org/PR31710

llvm-svn: 293522
 2017-01-30 18:29:46 +00:00
Simon Pilgrim 0a5ab5c4db Use SelectionDAG::getBuildVector/getSplatBuildVector helper functions where possible. NFCI. 
llvm-svn: 293520
 2017-01-30 18:20:42 +00:00
Marcos Pividori d2406ea900 [libFuzzer] Implement TmpDir() for Windows. 
Differential Revision: https://reviews.llvm.org/D28977

llvm-svn: 293516
 2017-01-30 18:14:53 +00:00
Daniel Berlin a53a72243a NewGVN: Instead of changeToUnreachable, insert an instruction SimplifyCFG will turn into unreachable when it runs 
llvm-svn: 293515
 2017-01-30 18:12:56 +00:00
Matt Arsenault ee3f0acf20 AMDGPU: Make i32 uaddo/usubo legal 
llvm-svn: 293514
 2017-01-30 18:11:38 +00:00
Matt Arsenault 32e6bfa20f DAG: Fold fneg into compare with constant into the constant 
fcmp (fneg x), c, pred -> fcmp x, -c, (swap pred)

InstCombine already does this.

llvm-svn: 293512
 2017-01-30 17:57:28 +00:00
Krzysztof Parzyszek 49ffff12e5 [RDF] Extract the physical register information into a separate class 
llvm-svn: 293510
 2017-01-30 17:46:56 +00:00
Tom Stellard 7a19d56f73 Revert "AMDGPU/GlobalISel: Add support for simple shaders" 
This reverts commit r293503.

Revert while I investigate some of the buildbot failures.

llvm-svn: 293509
 2017-01-30 17:42:41 +00:00
Sanjay Patel 062c14af5c [InstCombine] use auto with obvious type; NFC 
llvm-svn: 293508
 2017-01-30 17:38:55 +00:00
Sanjay Patel 77732d5033 [InstCombine] enable (X <<nsw C1) >>s C2 --> X <<nsw (C1-C2) for vectors with splat constants 
llvm-svn: 293507
 2017-01-30 17:19:32 +00:00
David Blaikie a66696f210 unique_ptrify some containers in GlobalISel::RegisterBankInfo 
To simplify/clarify memory ownership, make leaks (as one was found/fixed
recently) harder to write, etc.

(also, while I was there - removed a duplicate lookup in a container)

llvm-svn: 293506
 2017-01-30 17:13:56 +00:00
Matt Arsenault 41c1499504 AMDGPU: Fix atomic_inc/atomic_dec + ds_swizzle not being divergent 
llvm-svn: 293504
 2017-01-30 17:09:47 +00:00
Tom Stellard e48f60aec8 AMDGPU/GlobalISel: Add support for simple shaders 
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.

Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm

Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris

Differential Revision: https://reviews.llvm.org/D26730

llvm-svn: 293503
 2017-01-30 17:09:15 +00:00
Daniel Berlin e19f0e01a8 Revert "NewGVN: Make unreachable blocks be marked with unreachable" 
This reverts commit r293196

Besides making things look nicer, ATM, we'd like to preserve analysis
more than we'd like to destroy the CFG.  We'll probably revisit in the future

llvm-svn: 293501
 2017-01-30 17:06:55 +00:00
Simon Pilgrim 098998aef0 [X86][SSE] Add support for combining PINSRW+ASSERTZEXT+PEXTRW patterns with target shuffles 
llvm-svn: 293500
 2017-01-30 16:58:34 +00:00
Matt Arsenault 0c687390fe DAG: Constant fold fp16_to_fp/fp16_to_fp 
This fixes emitting conversions of constants on targets
without legal f16 that need to use these for legalization.

llvm-svn: 293499
 2017-01-30 16:57:41 +00:00
Sanjay Patel 8e644c08ee [InstCombine] fixed to propagate 'exact' on lshr 
The original shift is bigger, so this may qualify as 'obvious', 
but here's an attempt at an Alive-based proof:

Name: exact
Pre: (C1 u< C2)
%a = shl i8 %x, C1
%b = lshr exact i8 %a, C2 
  =>
%c = lshr exact i8 %x, C2 - C1
%b = and i8 %c, ((1 << width(C1)) - 1) u>> C2

Optimization is correct!

llvm-svn: 293498
 2017-01-30 16:53:03 +00:00
Benjamin Kramer 585756568c [Coroutines] Add header guard to header that's missing one. 
llvm-svn: 293494
 2017-01-30 16:32:20 +00:00
Adam Nemet e7bdf227f6 [Inliner] Fold analysis remarks into missed remarks 
This significantly reduces the noise level of these messages.

llvm-svn: 293492
 2017-01-30 16:22:45 +00:00
Krzysztof Parzyszek b561cf953a [RDF] Add phis for entry block live-ins (in addition to function live-ins) 
llvm-svn: 293491
 2017-01-30 16:20:30 +00:00
Haicheng Wu f8dc2d8c8b [Inliner] Fix a comment to match the code. NFC. 
TotalAltCost => TotalSecondaryCost

Differential Revision: https://reviews.llvm.org/D29231

llvm-svn: 293490
 2017-01-30 16:15:14 +00:00
Sanjay Patel 1196d7cd7f [InstCombine] enable lshr(shl X, C1), C2 folds for vectors with splat constants 
llvm-svn: 293489
 2017-01-30 16:11:40 +00:00
Rafael Espindola e0eba3c493 Only print architecture dependent flags for that architecture. 
Different architectures can have different meaning for flags in the
SHF_MASKPROC mask, so we should always check what the architecture use
before checking the flag.

NFC for now, but will allow fixing the value of an xmos flag.

llvm-svn: 293484
 2017-01-30 15:38:43 +00:00
Benjamin Kramer 73564981fe [Hexagon] Make header self-contained. 
llvm-svn: 293482
 2017-01-30 14:55:33 +00:00
Asaf Badouh e11d2d73bf [X86][MCU] Minor bug fix for r293469 + test case 
llvm-svn: 293478
 2017-01-30 13:14:37 +00:00
Marek Olsak e81adb52b1 AMDGPU: Remove a useless VI SMRD pattern 
Summary: already covered by complex patterns

Reviewers: arsenm, nhaehnle, tstellarAMD

Subscribers: kzhuravl, wdng, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D28995

llvm-svn: 293477
 2017-01-30 12:25:14 +00:00
Marek Olsak 8e93529020 AMDGPU: Fix assembler encoding for EXP instructions on VI 
Reviewers: arsenm, tstellarAMD

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D28992

llvm-svn: 293476
 2017-01-30 12:25:03 +00:00
Daniel Berlin 9d8a335ce0 Revert "[MemorySSA] Revert r293361 and r293363, as the tests fail under asan." 
This reverts commit r293471, reapplying r293361 and r293363 with a fix
for an out-of-bounds read.

llvm-svn: 293474
 2017-01-30 11:35:39 +00:00
Sam McCall b9d6c10c2d [MemorySSA] Revert r293361 and r293363, as the tests fail under asan. 
llvm-svn: 293471
 2017-01-30 09:19:50 +00:00
Kristof Beyls 65a12c012f [GlobalISel] Add support for indirectbr 
Differential Revision: https://reviews.llvm.org/D28079

llvm-svn: 293470
 2017-01-30 09:13:18 +00:00
Asaf Badouh 53713df0c2 [X86][MCU] replace select with bit manipulation instead of branches 
Differential Revision: https://reviews.llvm.org/D28354


 

llvm-svn: 293469
 2017-01-30 08:16:59 +00:00
Craig Topper f6df4a6978 [AVX-512] Remove duplicate CodeGenOnly patterns for scalar register broadcast. We can use COPY_TO_REGCLASS like AVX does. 
This causes stack spill slots be oversized sometimes, but the same should already be happening with AVX.

llvm-svn: 293464
 2017-01-30 06:59:06 +00:00
Sam McCall a682dfb3e5 Include LLVMDumpValue in release builds. 
This part of the C API is still used in language bindings.

llvm-svn: 293460
 2017-01-30 05:40:52 +00:00
Jonas Paulsson 3f71d6a38e [LoopVectorize] Improve getVectorCallCost() getScalarizationOverhead() call. 
By calling getScalarizationOverhead with the CallInst instead of the types of
its arguments, we make sure that only unique call arguments are added to the
scalarization cost.

getScalarizationOverhead() is extended to handle calls by only passing on the
actual call arguments (which is not all the operands).

This also eliminates a wrapper function with the same name.

review: Hal Finkel
llvm-svn: 293459
 2017-01-30 05:38:05 +00:00
Craig Topper 0265a39472 [AVX-512] Remove KSET0B/KSET1B in favor of the patterns that select KSET0W/KSET1W for v8i1. 
llvm-svn: 293458
 2017-01-30 05:37:47 +00:00
Davide Italiano 6c77de0367 [MemorySSA] Correct an assertion surrounding with parentheses. 
llvm-svn: 293453
 2017-01-30 03:16:43 +00:00
Craig Topper 3b7e823f92 [AVX-512] Don't reuse VSHLI/VSRLI for mask register shifts. VSHLI/VSHRI shift within elements while KSHIFT moves whole elements. 
llvm-svn: 293448
 2017-01-30 00:06:01 +00:00
Chris Ray 30b3fafb94 [X86][Disassembler] Added SALC instruction 
Reviewers: joe.abbey, craig.topper

Reviewed By: craig.topper

Subscribers: majnemer, llvm-commits

Differential Revision: https://reviews.llvm.org/D29201

llvm-svn: 293447
 2017-01-29 23:02:47 +00:00
Craig Topper db919caf1b [AVX-512] Fix lowering for mask register concatenation with undef in the lower half. 
Previously this test case fired an assertion in getNode because we tried to create an insert_subvector with both input types the same size and the index pointing to half the vector width.

llvm-svn: 293446
 2017-01-29 22:53:33 +00:00