de36afc1fe
testcase for PR4466
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llvm-svn: 74367
2009-06-27 01:33:35 +00:00
5285817490
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
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llvm-svn: 74355
2009-06-26 23:13:13 +00:00
d3b930d426
Add some testcases for some of the recent ScalarEvolution bug fixes.
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llvm-svn: 74353
2009-06-26 22:54:11 +00:00
3aaa751712
Thumb-2 tests
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llvm-svn: 74345
2009-06-26 22:37:07 +00:00
b5c2639f83
remove unwind info, add test for asmprinting of jump table labels with (%rip)
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llvm-svn: 74337
2009-06-26 22:16:49 +00:00
07b016856d
Add x86 support for 'n' inline asm modifier. This will be handled target independently as part of MC work.
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llvm-svn: 74336
2009-06-26 22:00:19 +00:00
aa294c5593
Thumb-2 has CLZ.
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llvm-svn: 74322
2009-06-26 20:47:43 +00:00
35ee722d42
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
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llvm-svn: 74321
2009-06-26 20:45:56 +00:00
a720af1370
More spelling Count as count.
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llvm-svn: 74306
2009-06-26 18:35:07 +00:00
6b1678d5d8
Spell Count as count.
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llvm-svn: 74298
2009-06-26 18:21:54 +00:00
3bd42afebe
Add Thumb-2 tests.
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llvm-svn: 74295
2009-06-26 18:10:30 +00:00
5960e6d974
ADC used to implement adde should use "adcs" opcode instead of "adc".
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llvm-svn: 74293
2009-06-26 18:07:25 +00:00
34f7ede9e7
ORN and BIC tests.
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llvm-svn: 74289
2009-06-26 16:20:06 +00:00
0377f737ff
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
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Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
llvm-svn: 74288
2009-06-26 16:10:07 +00:00
7779156b39
Fix tests: Count -> count.
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llvm-svn: 74282
2009-06-26 07:05:57 +00:00
34c8c7414f
Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates.
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llvm-svn: 74276
2009-06-26 05:59:16 +00:00
07025e2c02
Fix spelling of 'count'
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llvm-svn: 74249
2009-06-26 01:33:02 +00:00
97727a61f9
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
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llvm-svn: 74228
2009-06-25 23:34:10 +00:00
16f357cccf
Use MVN for ~t2_so_imm immediates.
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llvm-svn: 74223
2009-06-25 23:11:21 +00:00
722c6e1b70
Don't grep the -debug output. This isn't the way to test changes.
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llvm-svn: 74211
2009-06-25 21:59:32 +00:00
a4194b1082
down with unwind info :)
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llvm-svn: 74206
2009-06-25 21:48:17 +00:00
c7ea8df67e
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
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llvm-svn: 74200
2009-06-25 20:59:23 +00:00
83f979a48b
Add Thumb2 pc relative add.
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llvm-svn: 74141
2009-06-24 23:47:58 +00:00
ff1a4a7271
We should run these tests as well.
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llvm-svn: 74121
2009-06-24 21:36:26 +00:00
01d5049dc2
unwind info not needed.
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llvm-svn: 74112
2009-06-24 19:48:04 +00:00
d76d0aa68a
Move thumb and thumb2 tests into separate directories.
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llvm-svn: 74068
2009-06-24 06:36:07 +00:00
38f2453817
Fix support for inline asm input / output operand tying when operand spans across multiple registers (e.g. two i64 operands in 32-bit mode).
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llvm-svn: 74053
2009-06-24 02:05:51 +00:00
f19aeec3f5
Extend ScalarEvolution's multiple-exit support to compute exact
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trip counts in more cases.
Generalize ScalarEvolution's isLoopGuardedByCond code to recognize
And and Or conditions, splitting the code out into an
isNecessaryCond helper function so that it can evaluate Ands and Ors
recursively, and make SCEVExpander be much more aggressive about
hoisting instructions out of loops.
test/CodeGen/X86/pr3495.ll has an additional instruction now, but
it appears to be due to an arbitrary register allocation difference.
llvm-svn: 74048
2009-06-24 01:18:18 +00:00
4983e4550e
Proper patterns for thumb2 shift and rotate instructions.
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llvm-svn: 73987
2009-06-23 19:39:13 +00:00
2e076c4e02
Add support for ARM's Advanced SIMD (NEON) instruction set.
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This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
16ee19738c
It's coalescer, not coaleser.
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llvm-svn: 73902
2009-06-22 21:09:17 +00:00
4582530a2c
For Darwin on ARMv6 and newer, make register r9 available for use as a
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caller-saved register.
llvm-svn: 73901
2009-06-22 21:01:46 +00:00
8cbbc7944d
Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced.
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llvm-svn: 73898
2009-06-22 20:49:32 +00:00
3d75d6af57
hasFP should return true if frame address is taken.
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llvm-svn: 73893
2009-06-22 18:38:48 +00:00
6ead59f8ed
Fix PR4185.
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Handle FpSET_ST0_80 being used when ST0 is still alive.
llvm-svn: 73850
2009-06-21 12:02:51 +00:00
7d2b049404
change TLS_ADDR lowering to lower to a real mem operand, instead of matching as
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a global with that gets printed with the :mem modifier. All operands to lea's
should be handled with the lea32mem operand kind, and this allows the TLS stuff
to do this. There are several better ways to do this, but I went for the minimal
change since I can't really test this (beyond make check).
This also makes the use of EBX explicit in the operand list in the 32-bit,
instead of implicit in the instruction.
llvm-svn: 73834
2009-06-20 20:38:48 +00:00
1771a852f0
no need for unwind info
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llvm-svn: 73832
2009-06-20 19:48:26 +00:00
fbc9778a1b
no need for unwind info here.
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llvm-svn: 73831
2009-06-20 19:43:09 +00:00
c6a8d0dbe9
Fix PR4419: handle defs of partial uses.
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llvm-svn: 73816
2009-06-20 04:34:51 +00:00
cc31110b95
Re-apply r73718, now that the fix in r73787 is in, and add a
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hand-crafted testcase which demonstrates the bug that was exposed
in 254.gap.
llvm-svn: 73793
2009-06-19 23:23:27 +00:00
b4b20bbb7d
Enable arm pre-allocation load / store multiple optimization pass.
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llvm-svn: 73791
2009-06-19 23:17:27 +00:00
86076c9e30
Revert 73718. It's breaking 254.gap.
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llvm-svn: 73783
2009-06-19 21:15:06 +00:00
2fc939c809
Fix for PR2484: add an SSE1 pattern for a shuffle we normally prefer to
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handle with an SSE2 instruction.
llvm-svn: 73760
2009-06-19 07:00:55 +00:00
d984158320
Mark a few Thumb instructions commutable; just happened to spot this
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while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
llvm-svn: 73746
2009-06-19 01:43:08 +00:00
de9e36a74e
On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
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llvm-svn: 73720
2009-06-18 20:37:15 +00:00
8c9ac59455
Generalize LSR's OptimizeSMax to handle unsigned max tests as well
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as signed max tests. Along with r73717, this helps CodeGen avoid
emitting code for a maximum operation for this class of loop.
llvm-svn: 73718
2009-06-18 20:23:18 +00:00
a0348809b6
Remove the code from IVUsers that attempted to handle
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casted induction variables in cases where the cast
isn't foldable. It ended up being a pessimization in
many cases. This could be fixed, but it would require
a bunch of complicated code in IVUsers' clients. The
advantages of this approach aren't visible enough to
justify it at this time.
llvm-svn: 73706
2009-06-18 16:54:06 +00:00
02bb33c58d
Initial support for some Thumb2 instructions.
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Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
llvm-svn: 73622
2009-06-17 18:13:58 +00:00
469e8217d4
Make the test target-neutral
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llvm-svn: 73547
2009-06-16 20:25:25 +00:00
5d28cb204f
GNU as refuses to assemble "pop {}" instruction. Do not emit such
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(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).
llvm-svn: 73529
2009-06-16 18:49:08 +00:00
Chris Lattner