bcbae01797
CMake: Added asm file to x86_64 MSVC build.
...
llvm-svn: 78807
2009-08-12 15:54:28 +00:00
a5fdfac6ca
register naming cleanup (s/ip/r12/)
...
llvm-svn: 78806
2009-08-12 15:21:13 +00:00
9a6cf91261
Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple
...
pair instead of from a virtual method on TargetMachine. This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use
TargetAsmInfo.
llvm-svn: 78802
2009-08-12 07:22:17 +00:00
ee01029811
Move immediate constant predicate templates from the Blackfin target to MathExtras.h
...
llvm-svn: 78793
2009-08-12 06:22:07 +00:00
bb2af3555c
Shrink Thumb2 movcc instructions.
...
llvm-svn: 78790
2009-08-12 05:17:19 +00:00
81348021b1
Remove another Darwin assembler workaround.
...
llvm-svn: 78779
2009-08-12 02:07:19 +00:00
fd10869d4b
80 col violation.
...
llvm-svn: 78778
2009-08-12 02:03:03 +00:00
608d92c943
Remove an Darwin assembler workaround.
...
llvm-svn: 78777
2009-08-12 01:56:42 +00:00
1e6c2a1c17
Shrink ADDS, ADC, RSB, and SUBS.
...
llvm-svn: 78776
2009-08-12 01:49:45 +00:00
f042eadd1e
Add missing chain operands for VLD* and VST* instructions.
...
Set "mayLoad" and "mayStore" on the load/store instructions.
llvm-svn: 78761
2009-08-12 00:49:01 +00:00
117c9e8497
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first.
...
llvm-svn: 78759
2009-08-12 00:36:31 +00:00
2b083cf989
prune #include
...
llvm-svn: 78749
2009-08-11 23:07:27 +00:00
b9c1d6c86e
prune #includage.
...
llvm-svn: 78748
2009-08-11 23:06:16 +00:00
96db1abb77
fix CodeGen/PowerPC/2007-01-15-AsmDialect.ll, fallout from r78742
...
llvm-svn: 78747
2009-08-11 23:03:40 +00:00
1e9097e36a
change the -x86-asm-syntax=intel/att flag to be in X86TAI
...
instead of X86 Subtarget. This elimianates dependencies on
X86Subtarget from X86TAI.
llvm-svn: 78746
2009-08-11 23:01:09 +00:00
f6a9d06241
Shrinkify Thumb2 r = add sp, imm.
...
llvm-svn: 78745
2009-08-11 23:00:31 +00:00
97868fe1b9
second half of commit.
...
llvm-svn: 78744
2009-08-11 22:52:15 +00:00
63d5be8a7b
pass "is64Bit" flag into PPC TAI ctors instead of a whole targetmachine.
...
llvm-svn: 78743
2009-08-11 22:51:34 +00:00
e655521a28
eliminate asmflavor from subtarget, PPCTAI is the only client
...
and each callee knows that it returns.
llvm-svn: 78742
2009-08-11 22:49:34 +00:00
abdcbc7ef2
Change the asmprinter to print the comment character before the
...
"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character. This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character. This also allows hoisting the darwin stuff up to the
shared TAI class.
llvm-svn: 78737
2009-08-11 22:39:40 +00:00
fd5defed1d
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
...
llvm-svn: 78736
2009-08-11 22:38:43 +00:00
54075a78b4
factorize more darwin TAI stuff. Note that this gives
...
darwin/arm support for .no_dead_strip
llvm-svn: 78734
2009-08-11 22:31:42 +00:00
526bcd461a
X86/AsmParser: Mark MOV64GSrm, MOV64FSrm, GS_MOV32rm, FS_MOV32rm as codegen only.
...
llvm-svn: 78733
2009-08-11 22:24:40 +00:00
6747b39ca5
factorize darwin ProtectedDirective and SetDirective.
...
llvm-svn: 78732
2009-08-11 22:22:44 +00:00
c4f8ea4ccb
Add 'isCodeGenOnly' bit to Instruction .td records.
...
- Used to mark fake instructions which don't correspond to an actual machine
instruction (or are duplicates of a real instruction). This is to be used for
"special cases" in the .td files, which should be ignored by things like the
assembler and disassembler. We still need a good solution to handle pervasive
duplication, like with the Int_ instructions.
- Set the bit on fake "mov 0" style instructions, which allows turning an
assembler matcher warning into a hard error.
- -2 FIXMEs.
llvm-svn: 78731
2009-08-11 22:17:52 +00:00
d832c8e87c
all darwin targets have .space and .zerofill, pull up.
...
llvm-svn: 78730
2009-08-11 22:17:31 +00:00
f710f71839
eliminate template from arm TAI
...
llvm-svn: 78729
2009-08-11 22:14:59 +00:00
374d5770f0
fix a bug I introduced in r78724 that caused failures in:
...
CodeGen/X86/dll-linkage.ll & CodeGen/X86/mingw-alloca.ll
llvm-svn: 78728
2009-08-11 22:12:58 +00:00
7faf1fd9a0
move LCOMMDirective = "\t.lcomm\t" up to DarwinTAI, eliminate
...
template in PPC backend for TAI.
llvm-svn: 78727
2009-08-11 22:06:07 +00:00
c6daf8f17c
Fix warnings.
...
llvm-svn: 78725
2009-08-11 21:59:30 +00:00
0909918514
eliminate the X86TargetAsmInfo template.
...
llvm-svn: 78724
2009-08-11 21:57:08 +00:00
f0e62eb78f
Added ADD instructions with rAX as one parameter to the Intel instruction
...
tables.
llvm-svn: 78721
2009-08-11 21:26:06 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
...
llvm-svn: 78717
2009-08-11 21:11:32 +00:00
e431871851
llvm-mc/AsmParser: Allow target to specific a comment delimiter, which will be
...
used to strip hard coded comments out of .td assembly strings.
llvm-svn: 78716
2009-08-11 20:59:47 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
2c30970b22
pass the TargetTriple down from each target ctor to the
...
LLVMTargetMachine ctor. It is currently unused.
llvm-svn: 78711
2009-08-11 20:42:37 +00:00
67e5ea2726
now that JumpTableDirective can differentate picness itself, MIPS TAI
...
no longer needs a targetmachine to initialize itself.
llvm-svn: 78710
2009-08-11 20:32:51 +00:00
fe27130454
split "JumpTableDirective" (an existing hack) into a PIC and nonPIC
...
version. This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.
The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.
llvm-svn: 78709
2009-08-11 20:30:58 +00:00
841850ed26
Add Thumb2 eh_sjlj_setjmp implementation
...
llvm-svn: 78701
2009-08-11 19:42:21 +00:00
1d5350c08f
fix GetInstSizeInBytes for eh_sjlj_setjmp
...
llvm-svn: 78683
2009-08-11 17:08:15 +00:00
ab2460c066
move some 32-bit instrs to x86instrinfo.td
...
llvm-svn: 78680
2009-08-11 16:58:39 +00:00
eda08015ee
This void is implicit in C++.
...
llvm-svn: 78678
2009-08-11 16:03:08 +00:00
7c50c9bd63
Tidy #includes.
...
llvm-svn: 78677
2009-08-11 16:02:12 +00:00
aa3fb65349
Simplify this code. The case where one class is GR64RegClass and the
...
other is a subclass of it is effectively handled by the prior tests.
llvm-svn: 78676
2009-08-11 15:59:48 +00:00
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
...
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
74eb9e7bfd
Move ~ARMConstantPoolValue() to the .cpp file to avoid needing to include <cstdlib> in the header.
...
llvm-svn: 78665
2009-08-11 15:26:27 +00:00
806845daec
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
...
llvm-svn: 78659
2009-08-11 09:37:40 +00:00
3606467709
Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
...
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.
llvm-svn: 78658
2009-08-11 08:52:18 +00:00
d4d352c663
80 column violation.
...
llvm-svn: 78657
2009-08-11 08:47:46 +00:00
192d7c0752
Cosmetic changes.
...
llvm-svn: 78655
2009-08-11 07:36:14 +00:00
6e62e93a8d
Adding a blank line back.
...
llvm-svn: 78654
2009-08-11 07:32:58 +00:00
12842f9865
Use vAny type to get rid of Neon intrinsics that differed only in whether
...
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
71527c1493
llvm-mc/X86: Parse '*' correctly (in the way the matcher expects).
...
llvm-svn: 78642
2009-08-11 05:00:25 +00:00
dd4103b55b
Fixed more problems caused by 78142.
...
Passing of indirect arguments starts after return value on the callee's frame.
llvm-svn: 78635
2009-08-11 01:51:55 +00:00
741a9c7bf6
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
...
llvm-svn: 78632
2009-08-11 01:15:26 +00:00
5cfb60ffc7
Added the x86 INT instructions; both the special-case INT 3 and the general-case
...
INT i8. These instructions are only for interpretation by disassemblers, not
for emission, so they do not as yet have patterns.
llvm-svn: 78630
2009-08-11 01:09:06 +00:00
b80734bb15
Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings.
...
llvm-svn: 78629
2009-08-11 01:07:38 +00:00
9382d5ac05
Add stdlib.h
...
llvm-svn: 78627
2009-08-11 00:20:00 +00:00
693e36a3e8
SjLj based exception handling unwinding support. This patch is nasty, brutish
...
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
llvm-svn: 78625
2009-08-11 00:09:57 +00:00
475f8a4fa2
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
...
llvm-svn: 78622
2009-08-10 23:56:04 +00:00
733a64db57
Fix a bug where DAGCombine was producing an illegal ConstantFP
...
node after legalize, and remove the workaround code from the
ARM backend.
llvm-svn: 78615
2009-08-10 23:15:10 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
d91dceea0f
Whitespace, 80-column, and isTwoAddress -> Constraints = "" changes.
...
No functional change.
llvm-svn: 78608
2009-08-10 22:37:37 +00:00
85b5b027f7
Use NEON for single-precision int<->FP conversions.
...
llvm-svn: 78604
2009-08-10 22:17:39 +00:00
148e9f0d3f
Do not rely on magic "llvm.dbg.*" global variable name to find debug info.
...
PIC16 developers, please verify.
llvm-svn: 78603
2009-08-10 22:11:20 +00:00
458c91732c
Fix up whitespace, remove commented out code.
...
llvm-svn: 78600
2009-08-10 21:48:58 +00:00
e4f79d140d
llvm-mc/AsmParser: Disambiguate i64i8imm.
...
llvm-svn: 78598
2009-08-10 21:06:41 +00:00
aeb1feb67a
llvm-mc/AsmParser: Allow .td users to redefine the names of the methods to call
...
on target specific operands for testing class membership and converting to
MCInst operands.
llvm-svn: 78597
2009-08-10 21:00:45 +00:00
3e77df2bcd
SimpleValueType-ify a few more methods on TargetLowering.
...
llvm-svn: 78595
2009-08-10 20:46:15 +00:00
f72c13bdf5
Handle the constantfp created during post-legalization dag combiner phase.
...
llvm-svn: 78594
2009-08-10 20:25:59 +00:00
246617857f
Continue the SimpleValueType-ification.
...
llvm-svn: 78593
2009-08-10 20:18:46 +00:00
0afe2cc097
llvm-mc/AsmMatcher: Fix thinko, Mem isn't a subclass of Imm.
...
llvm-svn: 78587
2009-08-10 19:08:02 +00:00
c30530d105
Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.
...
llvm-svn: 78584
2009-08-10 18:56:59 +00:00
17410a4b92
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record
...
structure.
llvm-svn: 78581
2009-08-10 18:41:10 +00:00
6c20391d38
split MachO section handling stuff out to its out .h/.cpp file.
...
llvm-svn: 78576
2009-08-10 18:15:01 +00:00
fbcafd4c6c
arm only needs to emit one .align directive for hidden nlp's, not one
...
per pointer.
llvm-svn: 78574
2009-08-10 18:02:16 +00:00
292472d3d3
make sure that arm nonlazypointers are aligned properly
...
llvm-svn: 78573
2009-08-10 18:01:34 +00:00
ec64b73712
Fix a weird ppc64-specific link error during an llvm-gcc build:
...
ld: bad offset (0x00000091) for lo14 instruction pic-base fix-up in ___popcountdi2 from libgcc/./_popcountsi2_s.o
The problem is that the non lazy symbol pointers need to be 8 byte aligned
on ppc64 and .section doesn't have an implicit alignment like ".non_lazy_symbol_pointer"
does.
llvm-svn: 78572
2009-08-10 17:58:51 +00:00
7b01bf6125
fix some warnings for the MSVC build, by Yonggang Luo!
...
llvm-svn: 78571
2009-08-10 17:35:42 +00:00
62e053b790
Checkpoint scheduling itinerary changes.
...
llvm-svn: 78564
2009-08-10 15:56:13 +00:00
5bb93ce769
Watch out for empty BB.
...
llvm-svn: 78562
2009-08-10 08:10:13 +00:00
8a640ae504
rev, rev16, and revsh do not set CPSR.
...
llvm-svn: 78561
2009-08-10 07:58:45 +00:00
f16a1d5b79
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
...
llvm-svn: 78560
2009-08-10 07:20:37 +00:00
1f5bee14a1
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
...
llvm-svn: 78559
2009-08-10 06:57:42 +00:00
092b701a2c
Add support for folding loads / stores into 16-bit moves used by Thumb2.
...
llvm-svn: 78558
2009-08-10 06:32:05 +00:00
55c014a9f3
80 col violation.
...
llvm-svn: 78557
2009-08-10 05:51:48 +00:00
f5b73869f2
Use tMOVgpr2gpr instead of t2MOVr.
...
llvm-svn: 78556
2009-08-10 05:49:43 +00:00
51cbd2d6c4
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
...
llvm-svn: 78550
2009-08-10 02:37:24 +00:00
5b4c308f0c
Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
...
llvm-svn: 78549
2009-08-10 02:06:53 +00:00
cb307a27bf
Make the big switch: Change MCSectionMachO to represent a section *semantically*
...
instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
llvm-svn: 78547
2009-08-10 01:39:42 +00:00
6e046f4291
Use abs64 instead abs; some platforms don't have a 64-bit abs overload. Noticed by Yonggang Luo!
...
llvm-svn: 78543
2009-08-09 22:37:07 +00:00
d461c1c559
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
...
llvm-svn: 78540
2009-08-09 19:17:19 +00:00
8e33cb2de1
llvm-mc/AsmParser: Implement user defined super classes.
...
- We can now discriminate SUB32ri8 from SUB32ri, for example.
llvm-svn: 78530
2009-08-09 07:20:21 +00:00
447c4ab91d
Extend comment on ParserMatchClass .td field, and add some missing
...
classes for X86.
llvm-svn: 78524
2009-08-09 06:00:04 +00:00
c32aa060bd
llvm-mc/AsmParser: Define match classes in the .td file.
...
-2 FIXMEs.
llvm-svn: 78523
2009-08-09 05:18:30 +00:00
591105c540
sink the 'name' and 'isdirective' state out of MCSection into its derived classes.
...
This totally optimizes PIC16 sections by not having an 'isdirective' bit anymore!! ;-)
llvm-svn: 78517
2009-08-08 23:39:42 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
...
'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
3219d85f16
add a note about dead zero extends.
...
llvm-svn: 78511
2009-08-08 22:46:59 +00:00
1cb9396f4f
1. Make MCSection an abstract class.
...
2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
llvm-svn: 78510
2009-08-08 22:41:53 +00:00
7dfa9f2e56
Add crc32 instruction and intrinsics. Add a new class of prefix
...
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.
New test.
llvm-svn: 78508
2009-08-08 21:55:08 +00:00
e2dc8a46e9
Add support for READCYCLECOUNTER in Blackfin back-end.
...
llvm-svn: 78506
2009-08-08 21:42:22 +00:00
26cc5b78d0
add new PIC16Section class, this time hopefully not breaking the build :)
...
llvm-svn: 78505
2009-08-08 21:37:01 +00:00
66f4f54e8a
llvm-mc/AsmMatcher: Switch token matching to use the new string matcher.
...
Also, redefined MatchRegisterName to just return the register value or a
sentinel, to simplify the generated code.
llvm-svn: 78504
2009-08-08 21:22:41 +00:00
59410aaea6
Revert r78501, it doesn't build.
...
--- Reverse-merging r78501 into '.':
U lib/Target/PIC16/PIC16TargetObjectFile.cpp
D lib/Target/PIC16/PIC16Section.h
llvm-svn: 78503
2009-08-08 21:12:40 +00:00
4a4e4487fc
make PIC16 create its own custom MCSection.
...
llvm-svn: 78501
2009-08-08 20:55:25 +00:00
245fdfb9c3
make target-specific TLOF impls (except PIC16) create target-specific
...
MCSection instances.
llvm-svn: 78500
2009-08-08 20:52:13 +00:00
c9ea8fddb2
eliminate TargetLoweringObjectFileSparc in favor of a TAI hook.
...
A TAI hook is appropriate in this case because this is just an
asm syntax issue, not a semantic difference. TLOF should model
the semantics of the section.
llvm-svn: 78498
2009-08-08 20:43:12 +00:00
36d04ec972
give pic16 a target-specific section creation name too
...
llvm-svn: 78496
2009-08-08 20:23:47 +00:00
ce7d14032b
now that getOrCreateSection is all object-file specific,
...
give the impls an object-file-specific name. In the future
they can take different arguments etc.
llvm-svn: 78495
2009-08-08 20:22:20 +00:00
302041d5c9
sink getOrCreateSection down into all the object file implementations,
...
now that they create *all* the sections.
llvm-svn: 78494
2009-08-08 20:14:13 +00:00
f6448f57e6
Use reloc_absolute_word_sext relocation for X86::MOV64(ri/mi)32 instructions,
...
since they are in 64 bit mode with i64immSExt32 imms. JIT is not affected since
it handles both word absolute relocations in the same way
llvm-svn: 78479
2009-08-08 17:47:41 +00:00
028f6dc4c2
Update CMake
...
llvm-svn: 78475
2009-08-08 17:03:13 +00:00
7167f33872
Add insert_elt / extract_elt patterns for v4f32 stuff.
...
Did anyone tests v4f32 ever?
llvm-svn: 78470
2009-08-08 14:06:07 +00:00
4218516f5d
Lane number should be printed w/o hash
...
llvm-svn: 78469
2009-08-08 14:05:53 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
...
llvm-svn: 78468
2009-08-08 13:35:48 +00:00
e372826523
move this fp select into a pattern
...
llvm-svn: 78464
2009-08-08 12:49:07 +00:00
541efcc5c4
llvm-mc/AsmMatcher: Improve match code.
...
- This doesn't actually improve the algorithm (its still linear), but the
generated (match) code is now fairly compact and table driven. Still need a
generic string matcher.
- The table still needs to be compressed, this is quite simple to do and should
shrink it to under 16k.
- This also simplifies and restructures the code to make the match classes more
explicit, in anticipation of resolving ambiguities.
llvm-svn: 78461
2009-08-08 07:50:56 +00:00
e2231070ff
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
...
so I generalized the class for VTRN in the .td file to handle all 3 of them.
llvm-svn: 78460
2009-08-08 06:13:25 +00:00
db46af0461
Implement Neon VTRN instructions. For now, anyway, these are selected
...
directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
llvm-svn: 78459
2009-08-08 05:53:00 +00:00
1be453b462
Add a skeleton Thumb2 instruction size reduction pass.
...
llvm-svn: 78456
2009-08-08 03:21:23 +00:00
2aa91cc2be
Code refactoring. No functionality change.
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llvm-svn: 78455
2009-08-08 03:20:32 +00:00
274fcbe43e
tADDhirr should target GPR, not tGPR.
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llvm-svn: 78454
2009-08-08 03:19:44 +00:00
4dc201eb64
I can type.
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llvm-svn: 78453
2009-08-08 02:54:37 +00:00
b94284b5e2
make printInstruction return void since its result is omitted. Make the
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error condition get trapped with an assert.
llvm-svn: 78449
2009-08-08 01:32:19 +00:00
b1692dc267
don't check the result of printInstruction anymore.
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llvm-svn: 78444
2009-08-08 00:05:42 +00:00
674ffc1e59
Do not generate 32-bit call on win64 when imm does not fit
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llvm-svn: 78443
2009-08-07 23:59:21 +00:00
742db6a6d4
Make NEON single-precision FP support the default for cortex-a8 (again).
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llvm-svn: 78430
2009-08-07 23:32:33 +00:00
e35472e3a9
remove a bunch of now-dead crud from the asmprinter and TAI interfaces.
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llvm-svn: 78428
2009-08-07 23:16:27 +00:00
d28a26dfab
Unbreak the stuff
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llvm-svn: 78425
2009-08-07 22:51:13 +00:00
a190c169bf
avoid this libcall with long inline expansion
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llvm-svn: 78420
2009-08-07 22:37:20 +00:00
23b28cb824
2 more vdup.32 cases
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llvm-svn: 78419
2009-08-07 22:36:50 +00:00
fb93be2b6f
A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR.
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llvm-svn: 78418
2009-08-07 22:36:37 +00:00
fe3bdb4b6f
Reformatting of lines. Put multiple DEBUG statements under one DEBUG statement.
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llvm-svn: 78411
2009-08-07 21:33:25 +00:00
6e130db3b7
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
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llvm-svn: 78410
2009-08-07 21:19:10 +00:00
15b8037034
llvm-mc/AsmMatcher: Tweaks in response to feedback.
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llvm-svn: 78404
2009-08-07 20:33:39 +00:00
b64ec07ea6
This is done.
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llvm-svn: 78399
2009-08-07 19:34:52 +00:00
f0237b1aa6
Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode.
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llvm-svn: 78398
2009-08-07 19:34:35 +00:00
4c3b1ca5a0
Fix support to use NEON for single precision fp math.
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llvm-svn: 78397
2009-08-07 19:30:41 +00:00
54c847cd6c
Minor fixes to avoid using invalid debugloc.
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llvm-svn: 78383
2009-08-07 11:00:02 +00:00
24ee4d0aa4
Simplify code and avoid allocations.
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llvm-svn: 78382
2009-08-07 10:42:28 +00:00
cf18d6befb
Improve disabling of X86 AsmMatcher.
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llvm-svn: 78381
2009-08-07 09:06:38 +00:00
32d0bb4c4e
Disable X86 AsmMatcher for now, it is causing gcc-4.0 to run out of memory on
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i386-apple-darwin9. This presumably will get fixed once the generated code
improves.
llvm-svn: 78379
2009-08-07 08:45:03 +00:00
e10787e710
llvm-mc/AsmMatcher: Move to a slightly more sane matching design.
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- Still not very sane, but a least its not 60k lines on X86. :)
- In terms of correctness, currently some things are hard wired for X86, and we
still don't properly resolve ambiguities (this is ignoring the instructions
we don't even match due to funny .td stuff or other corner cases).
The high level changes:
1. Represent tokens which are significant for matching explicitly as separate
operands. This uniformly handles not only the instruction mnemonic, but
also 'signficiant' syntax like the '*' in "call * ...".
2. Separate the matching of operands to an instruction from the construction of
the MCInst. In theory this can be done during matching, but since the number
of variations is small I think it makes sense to decompose the problems.
3. Improved a few of the mechanisms to at least successfully flatten / tokenize
the assembly strings for PowerPC and ARM.
4. The comment at the top of AsmMatcherEmitter.cpp explains the approach I'm
moving towards for handling ambiguous instructions. The high-bit is to infer
a partial ordering of the operand classes (and force the user to specify one
if we can't) and use that to resolve ambiguities.
llvm-svn: 78378
2009-08-07 08:26:05 +00:00
82ff022ed2
Error out, rather than infinite looping, if constant island pass can't converge.
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llvm-svn: 78377
2009-08-07 07:35:21 +00:00
317bd7aab2
tBfar is bl, which clobbers LR.
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llvm-svn: 78370
2009-08-07 05:45:07 +00:00
003dc1fa5b
Run memsel inserter just before emit assembly to avoid tinkering by other passes.
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llvm-svn: 78369
2009-08-07 05:44:27 +00:00
a3a3453acf
These should be expanded
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llvm-svn: 78365
2009-08-07 02:17:44 +00:00
a6d0afcb74
Fix a bunch of namespace pollution.
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llvm-svn: 78363
2009-08-07 01:32:21 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
edfdd07a79
Output the new StructType constructor, which takes the context of the
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module as first argument.
llvm-svn: 78340
2009-08-06 21:31:35 +00:00
cd4688905f
Use DebugInfoFinder
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llvm-svn: 78334
2009-08-06 20:53:24 +00:00
0127031c20
Implement Neon VST[234] operations.
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llvm-svn: 78330
2009-08-06 18:47:44 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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llvm-svn: 78321
2009-08-06 16:52:47 +00:00
1ff90134a4
Fix several fixmes and clean up code by sinking *all* section
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creation activity into the target-specific subclasses of TLOF.
Before this, globals with explicit sections could be created by
the base class.
1. make getOrCreateSection protected, add a new getExplicitSectionGlobal
pure virtual method to assign sections to globals with a specified
section.
2. eliminate getSpecialCasedSectionGlobals, which is now PIC specific.
3. eliminate the getKindForNamedSection virtual method, which is
now just a static method for ELF.
4. Add implementions of getExplicitSectionGlobal for ELF/PECOFF/Darwin/PIC16.
They are now all detangled and understandable, woo! :)
llvm-svn: 78319
2009-08-06 16:39:58 +00:00
b29996eb23
go through PIC16TargetObjectFile to make sections instead of
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creating them directly in the pic16 asmprinter.
llvm-svn: 78317
2009-08-06 16:27:28 +00:00
d0439d0638
We need to sext global addresses in kernel code model, not zext
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llvm-svn: 78299
2009-08-06 11:23:24 +00:00
130e2c7aed
Fix a bug in x86's PreprocessForRMW logic that was exposed
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by aggressive chain operand optimization. UpdateNodeOperands
does not modify the node in place if it would result in
a node identical to an existing node.
llvm-svn: 78297
2009-08-06 09:22:57 +00:00
82db9891fa
Missed part of recent kernel codemodel tweaks
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llvm-svn: 78293
2009-08-06 09:11:19 +00:00
488db94e7b
Neon does not actually have VLD{234}.64 instructions.
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These operations will have to be synthesized from other instructions.
llvm-svn: 78263
2009-08-06 00:24:27 +00:00
e148ceaf65
Add a new pre-allocation pass to assign adjacent registers for Neon instructions
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that have that constraint. This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.
llvm-svn: 78256
2009-08-05 23:12:45 +00:00
741ea0d7fd
Better handle kernel code model. Also, generalize the things and fix one
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subtle bug with small code model.
llvm-svn: 78255
2009-08-05 23:01:26 +00:00
77f33b71c7
Use GR32 for copies between GR32_NOSP and GR32_NOREX, as neither
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is a subset of the other, but both are subsets of GR32.
llvm-svn: 78250
2009-08-05 22:18:26 +00:00
e5b5d8fbb3
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
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llvm-svn: 78244
2009-08-05 21:02:22 +00:00
39fb546b9e
remove the 'DataSectionStartSuffix' and 'TextSectionStartSuffix' knobs.
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llvm-svn: 78242
2009-08-05 20:49:52 +00:00
ef98dbe3de
Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly
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hardfloat case.
llvm-svn: 78237
2009-08-05 20:15:19 +00:00
87cc2c2dce
hasSuperClass tests for a strict superset relation, rather than
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a superset relation. This code wants to test the regular superset
relation.
llvm-svn: 78236
2009-08-05 20:13:45 +00:00
ef42862ef5
Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv.
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llvm-svn: 78232
2009-08-05 19:40:16 +00:00
22ef75155e
Missed pieces for ARM HardFP ABI.
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Patch by Sandeep Patel!
llvm-svn: 78225
2009-08-05 19:04:42 +00:00
13937d8236
Use elf Object File directly
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llvm-svn: 78220
2009-08-05 18:13:04 +00:00
4cc1feff4f
Remove some dead code.
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llvm-svn: 78219
2009-08-05 18:12:37 +00:00
df7ea32af7
Enable the new no-SP register classes by default. This is to address
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PR4572. A few tests have some minor code regressions due to different
coalescing.
llvm-svn: 78217
2009-08-05 17:40:24 +00:00
9ede773c4e
Remove a redundant declaration.
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llvm-svn: 78216
2009-08-05 17:39:44 +00:00
be47ccffef
Convert bswap test to filecheck, add more test entries & convert stuff to filecheck
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llvm-svn: 78212
2009-08-05 16:50:53 +00:00
477fd55c9a
Fix a bug in the PIC16 backend.
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llvm-svn: 78211
2009-08-05 16:46:43 +00:00
21788bef7c
Disable NEON single-precision FP support for Cortex-A8, for now...
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llvm-svn: 78209
2009-08-05 16:40:57 +00:00
44c4417812
Remove dead code. MDNode and MDString are not Constant anymore.
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llvm-svn: 78207
2009-08-05 16:40:02 +00:00
2e627cb37f
Add memory versions of some instructions.
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Patch by Neale Ferguson!
llvm-svn: 78203
2009-08-05 16:16:11 +00:00
a307edbdd5
By default, for cortex-a8 use NEON for single-precision FP.
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llvm-svn: 78200
2009-08-05 16:01:19 +00:00
cb781cfe81
Special constants as destinations does not work as expected - drop the patterns.
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llvm-svn: 78191
2009-08-05 14:42:00 +00:00
ba3a342c89
Alpha: Get section directives right
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llvm-svn: 78189
2009-08-05 13:59:57 +00:00
de8b1b2e7d
Cleanup in dbg_stoppoint handling in CBE. Patch by Sandeep Patel.
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llvm-svn: 78182
2009-08-05 09:31:40 +00:00
68d8634871
Minor arm CBE fixes. Patch by Sandeep.
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llvm-svn: 78181
2009-08-05 09:31:07 +00:00
fe4ce2ae7a
Emit module-level inline asm for CBE.
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Patch by Sandeep Patel
llvm-svn: 78180
2009-08-05 09:29:56 +00:00
2b1dc9a783
- Remove custom handling of jumptables by the elf writter (this was
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a dirty hack and isn't need anymore since the last x86 code emitter patch)
- Add a target-dependent modifier to addend calculation
- Use R_X86_64_32S relocation for X86::reloc_absolute_word_sext
- Use getELFSectionFlags whenever possible
- fix getTextSection to use TLOF and emit the right text section
- Handle global emission for static ctors, dtors and Type::PointerTyID
- Some minor fixes
llvm-svn: 78176
2009-08-05 06:57:03 +00:00
e219be7346
80 col violations.
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llvm-svn: 78175
2009-08-05 06:41:25 +00:00
8c79569853
Teach X86FastISel how to handle CCValAssign::BCvt, which is used for
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MMX arguments. This fixes PR4684.
llvm-svn: 78163
2009-08-05 05:33:42 +00:00
d055488c72
Clarify common linkage and the requirements on it. Enforce
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them in the verifier.
llvm-svn: 78160
2009-08-05 05:21:07 +00:00
cbc7b26542
expose SectionKindForGlobal to curious clients, named as
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getKindForGlobal.
llvm-svn: 78156
2009-08-05 04:25:40 +00:00
85f60cc5a8
Oops. I didn't mean to commit this piece yet.
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llvm-svn: 78146
2009-08-05 02:47:13 +00:00
f9bbcd1afd
Major calling convention code refactoring.
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Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 01:29:28 +00:00
cbf1e16ad9
Remove an unnecessary flush in the CppBackend's output.
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llvm-svn: 78138
2009-08-05 01:06:38 +00:00
c6b5e8a5c5
Don't flush the raw_ostream between each MachineFunction. These flush
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calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.
llvm-svn: 78137
2009-08-05 00:49:25 +00:00
20f79e321e
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
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Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
llvm-svn: 78136
2009-08-05 00:49:09 +00:00
1b02ceeb41
1) Proper emit displacements for x86, using absolute relocations where necessary
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for ELF to work.
2) RIP addressing: Use SIB bytes for absolute relocations where RegBase=0,
IndexReg=0.
3) The JIT can get the real address of cstpools and jmptables during
code emission, fix that for object code emission
llvm-svn: 78129
2009-08-05 00:11:21 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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llvm-svn: 78126
2009-08-04 23:47:55 +00:00
a8720101b5
Replace dregsingle operand modifier with explicit escaped curly brackets.
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For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.
llvm-svn: 78109
2009-08-04 21:39:33 +00:00
f2dbd2e205
Restlyize to match other targets, fixes cmake build to boot.
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llvm-svn: 78105
2009-08-04 21:27:06 +00:00
783b65b546
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
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llvm-svn: 78104
2009-08-04 21:12:13 +00:00
cd450bbbe5
remove a random reference to subtarget. Even without this, we
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still get "intel syntax" instructions from llc with
-x86-asm-syntax=intel
llvm-svn: 78103
2009-08-04 21:12:08 +00:00
30bf625ac2
Add NEON single-precision FP support for fabs and fneg.
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llvm-svn: 78101
2009-08-04 20:39:05 +00:00
Oscar Fuentes