Commit Graph

3 Commits

Author SHA1 Message Date
Shiva Chen c3d0e89284 [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table
Resolving fixup_riscv_call by assembler when the linker relaxation diabled
and the function and callsite within the same compile unit.

And also adding static_assert after Infos array declaration
to avoid missing any new fixup in MCFixupKindInfo in the future.

Differential Revision: https://reviews.llvm.org/D47126

llvm-svn: 333487
2018-05-30 01:16:36 +00:00
Alex Bradbury 59136ffab1 [RISCV] Enable emission of alias instructions by default
This patch switches the default for -riscv-no-aliases to false
and updates all affected MC and CodeGen tests. As recommended in
D41071, MC tests use the canonical instructions and the CodeGen
tests use the aliases.

Additionally, for the f and d instructions with rounding mode,
the tests for the aliased versions are moved and tightened such
that they can actually detect if alias emission is enabled.
(see D40902 for context)

Differential Revision: https://reviews.llvm.org/D41225

Patch by Mario Werner.

llvm-svn: 320797
2017-12-15 09:47:01 +00:00
Alex Bradbury 9d3f12501a [RISCV] Add common fixups and relocations
%lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to 
ensure the appropriate fixups and relocations are generated. I've added an 
instruction format field which is used in RISCVMCCodeEmitter to, for 
instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup 
(RISC-V has two 12-bit immediate encodings depending on the instruction 
type).

Differential Revision: https://reviews.llvm.org/D23568

llvm-svn: 314389
2017-09-28 08:26:24 +00:00