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22576 Commits

Author SHA1 Message Date
Craig Topper c8c28d1ff0 Mark ISD::FMA as Legal instead of custom for x86 with FMA3/FMA4. Needed so that llvm.muladd can be converted to ISD::FMA for fp_contract. 
llvm-svn: 168413
 2012-11-21 05:36:24 +00:00
Jakub Staszak 59deec0132 Make calcLiveInMask method static. 
llvm-svn: 168409
 2012-11-21 00:59:34 +00:00
Jakub Staszak 6f58ce1678 Make isScratchReg and isFPCopy methods static. 
llvm-svn: 168407
 2012-11-21 00:50:57 +00:00
Jakub Staszak e2edeac1c1 Add obvious constantness. 
llvm-svn: 168396
 2012-11-20 23:32:32 +00:00
Jyotsna Verma c6f2465b5d Removing some unused instruction definitions from the Hexagon backend. 
llvm-svn: 168388
 2012-11-20 22:14:23 +00:00
Elena Demikhovsky fc4840fbed Intel OCL built-ins calling conventions now support MacOS 32-bit. 
llvm-svn: 168359
 2012-11-20 09:37:57 +00:00
Eli Friedman 30834940ec Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete Couperus. 
llvm-svn: 168240
 2012-11-17 01:52:46 +00:00
Akira Hatanaka ef83919b4c Initial implementation of MipsTargetLowering::isLegalAddressingMode. 
llvm-svn: 168230
 2012-11-17 00:25:41 +00:00
Weiming Zhao 9578222e0d Rename methods like PairSRegs() to createSRegpairNode() to meet our coding 
style requirement.

llvm-svn: 168229
 2012-11-17 00:23:35 +00:00
Weiming Zhao 8f56f88661 Remove hard coded registers in ARM ldrexd and strexd instructions 
This patch replaces the hard coded GPR pair [R0, R1] of
Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with
even/odd GPRPair reg class.
Similar to the lowering of atomic_64 operation.

llvm-svn: 168207
 2012-11-16 21:55:34 +00:00
Anton Korobeynikov 7d94f3bd7f Make sure FABS on v2f32 and v4f32 is legal on ARM NEON 
This fixes PR14359

llvm-svn: 168200
 2012-11-16 21:15:20 +00:00
Richard Osborne 9a43772783 Fix handling of aliases to functions. 
An alias to a function should use pc relative addressing.

llvm-svn: 168199
 2012-11-16 21:12:38 +00:00
Justin Holewinski 2c5ac70dd9 [NVPTX] Order global variables in def-use order before emiting them in the final assembly 
llvm-svn: 168198
 2012-11-16 21:03:51 +00:00
Joe Abbey cceda898b8 Using const cast to alleviate a warning. 
A PR is being filed to address some code issues here.

llvm-svn: 168185
 2012-11-16 19:38:42 +00:00
Duncan Sands d71b4e4568 Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris. 
llvm-svn: 168166
 2012-11-16 12:36:39 +00:00
Craig Topper 70601ba6f9 Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of vector types. 
llvm-svn: 168141
 2012-11-16 06:37:56 +00:00
Akira Hatanaka 907f5f0ca7 [mips] Fix delay slot filler so that instructions with register operand $1 are 
allowed in branch delay slot.

llvm-svn: 168131
 2012-11-16 02:39:34 +00:00
Eli Friedman e6385e61b5 Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missing 
case to vector legalization so this actually works.

Patch by Pete Couperus.  Fixes PR12540.

llvm-svn: 168107
 2012-11-15 22:44:27 +00:00
Akira Hatanaka 3bc1beb696 [mips] Add predicate HasFPIdx for floating-point indexed load instruction 
support and use it in place of HasMips32r2Or64.

llvm-svn: 168089
 2012-11-15 21:17:13 +00:00
Adhemerval Zanella bdface5699 PowerPC: Lowering floor intrinsic for Altivec 
This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and
llvm.nearbyint to Altivec instruction when using 4 single-precision
float vectors.

llvm-svn: 168086
 2012-11-15 20:56:03 +00:00
Akira Hatanaka 5fdeac3268 Add assertions in MipsLongBranch which check the size of basic blocks. 
llvm-svn: 168078
 2012-11-15 20:05:11 +00:00
Jakub Staszak f34e4fa7a6 Return 0 instead of false. 
llvm-svn: 168076
 2012-11-15 19:40:29 +00:00
Jakub Staszak 11d1aee6a2 Simplify code. 
llvm-svn: 168064
 2012-11-15 19:05:23 +00:00
Dmitri Gribenko 0011bbf985 Use empty parens for empty function parameter list instead of '(void)'. 
llvm-svn: 168049
 2012-11-15 16:51:49 +00:00
Craig Topper 323f614cd1 Revert changing FNEG of v4f32 to Expand. It's legal. 
llvm-svn: 168030
 2012-11-15 08:09:46 +00:00
Craig Topper bb7060584c Make FNEG and FABS of v4f32 Expand. 
llvm-svn: 168029
 2012-11-15 08:06:12 +00:00
Craig Topper c8a2adf1ca Make a bunch of floating point operations on vectors Expand so that instruction selection won't fail. 
llvm-svn: 168028
 2012-11-15 08:02:19 +00:00
Craig Topper 61d045781a Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics. 
llvm-svn: 168025
 2012-11-15 06:51:10 +00:00
Jakub Staszak f33e0f95b0 Remove unneeded #includes. 
llvm-svn: 168006
 2012-11-14 23:58:57 +00:00
NAKAMURA Takumi 5bbe0e18e9 NVPTXISelLowering.cpp: Fix warnings. [-Wunused-variable] 
llvm-svn: 168001
 2012-11-14 23:46:15 +00:00
Eric Christopher 950d8703b1 Remove the CellSPU port. 
Approved by Chris Lattner.

llvm-svn: 167984
 2012-11-14 22:09:20 +00:00
Jakub Staszak d17df318c0 Fix invalid asserts, use llvm_unreachable instead. 
llvm-svn: 167976
 2012-11-14 21:03:40 +00:00
Jyotsna Verma 6649360860 Added multiclass for post-increment load instructions. 
llvm-svn: 167974
 2012-11-14 20:38:48 +00:00
Benjamin Kramer 6293429b51 X86: Enable SSE memory intrinsics even when stack alignment is less than 16 bytes. 
The stack realignment code was fixed to work when there is stack realignment and
a dynamic alloca is present so this shouldn't cause correctness issues anymore.

Note that this also enables generation of AVX instructions for memset
under the assumptions:
- Unaligned loads/stores are always fast on CPUs supporting AVX
- AVX is not slower than SSE
We may need some tweaked heuristics if one of those assumptions turns out not to
be true.

Effectively reverts r58317. Part of PR2962.

llvm-svn: 167967
 2012-11-14 20:08:40 +00:00
Nadav Rotem 9f567c62f2 The code pattern "imm0_255_neg" is used for checking if an immediate value is a small negative number. 
This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of
a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag.

rdar://12028498

llvm-svn: 167963
 2012-11-14 19:39:15 +00:00
Justin Holewinski c6462aacd5 [NVPTX] Implement custom lowering of loads/stores for i1 
Loads from i1 become loads from i8 followed by trunc
Stores to i1 become zext to i8 followed by store to i8

Fixes PR13291

llvm-svn: 167948
 2012-11-14 19:19:16 +00:00
Jim Grosbach 6f1f41b1ae X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches. 
When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.

rdar://12700702

llvm-svn: 167937
 2012-11-14 18:04:47 +00:00
Craig Topper c4343f2c45 Set FFLOOR of vectors to expand to keep intruction selection from failing. 
llvm-svn: 167922
 2012-11-14 08:11:25 +00:00
Craig Topper a7f489d1ab Factor out an overly replicated typecast. No functional change. 
llvm-svn: 167916
 2012-11-14 06:41:09 +00:00
Craig Topper 54c45ab570 Set FFLOOR for vectors to expand on CellSPU to keep instruction selection from failing on llvm.floor of a vector. 
llvm-svn: 167914
 2012-11-14 05:56:30 +00:00
Anton Korobeynikov e42af3699b Use TARGET2 relocation for TType references on ARM. 
Do some cleanup of the code while here.

Inspired by patch by Logan Chien!

llvm-svn: 167904
 2012-11-14 01:47:00 +00:00
Ulrich Weigand 8557850053 Add (some) PowerPC TLS relocation types to ELF.h and 
generate them from PPCELFObjectWriter::getRelocTypeInner
as appropriate.

llvm-svn: 167864
 2012-11-13 19:24:36 +00:00
Ulrich Weigand 0f79500af5 Fix wrong PowerPC instruction opcodes for: 
- lwaux
 - lhzux
 - stbu

llvm-svn: 167863
 2012-11-13 19:21:31 +00:00
Ulrich Weigand a82389b3d0 Fix wrong PowerPC instruction encodings due to 
operand field name mismatches in:
 - AForm_3  (fmul, fmuls)
 - XFXForm_5 (mtcrf)
 - XFLForm (mtfsf)

llvm-svn: 167862
 2012-11-13 19:19:46 +00:00
Ulrich Weigand 0117718580 Fix instruction encoding for "bd(n)z" on PowerPC, 
by using a new instruction format BForm_1.

llvm-svn: 167861
 2012-11-13 19:15:52 +00:00
Ulrich Weigand 84ee76acfe Fix instruction encoding for "isel" on PowerPC, 
using a new instruction format AForm_4.

llvm-svn: 167860
 2012-11-13 19:14:19 +00:00
Manman Ren 0f3240d3a7 X86: when constructing VZEXT_LOAD from other loads, makes sure its output 
chain is correctly setup.

As an example, if the original load must happen before later stores, we need
to make sure the constructed VZEXT_LOAD is constrained to be before the stores.

rdar://12684358

llvm-svn: 167859
 2012-11-13 19:13:05 +00:00
Andrew Trick 108c88c5b7 misched: Allow subtargets to enable misched and dependent options. 
This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want to:
- Disable SelectionDAG scheduling (use the source order scheduler)
- Enable more aggressive coalescing (until we decide to always run the coalescer this way)
- Enable MachineScheduler pass itself.

Disabling PostRA sched may follow for some subtargets.

llvm-svn: 167826
 2012-11-13 08:47:29 +00:00
Jyotsna Verma ccfd77ef90 Test commit. 
Add a blank line.

llvm-svn: 167819
 2012-11-13 06:31:55 +00:00
Andrew Trick a7714a0ff9 misched: Target-independent support for load/store clustering. 
This infrastructure is generally useful for any target that wants to
strongly prefer two instructions to be adjacent after scheduling.

A following checkin will add target-specific hooks with unit
tests. Then this feature will be enabled by default with misched.

llvm-svn: 167742
 2012-11-12 19:40:10 +00:00