Commit Graph

284 Commits

Author SHA1 Message Date
Evan Cheng 9de7cfe3f4 Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ.
llvm-svn: 103692
2010-05-13 01:12:06 +00:00
Evan Cheng 79efd71962 Mark some pattern-less instructions as neverHasSideEffects.
llvm-svn: 103683
2010-05-13 00:16:46 +00:00
Evan Cheng 86eb22976f Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
llvm-svn: 103235
2010-05-07 02:04:02 +00:00
Evan Cheng ddc93c7e04 Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
llvm-svn: 103218
2010-05-07 00:24:52 +00:00
Evan Cheng 31cdcd46d6 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
llvm-svn: 103172
2010-05-06 06:36:08 +00:00
Eric Christopher 9feb1bb117 Revert r103156 since it was breaking the build bots.
Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td

llvm-svn: 103159
2010-05-06 02:29:06 +00:00
Evan Cheng 8f99a1c6b4 Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
llvm-svn: 103156
2010-05-06 01:52:03 +00:00
Anton Korobeynikov 4d36f8890f More fixes for itins
llvm-svn: 100662
2010-04-07 18:21:10 +00:00
Anton Korobeynikov ceb54d5ab0 Fix invalid itins for 32-bit varians of VMLAL and friends
llvm-svn: 100661
2010-04-07 18:21:04 +00:00
Anton Korobeynikov a248becd6c Fix itins for VABA
llvm-svn: 100657
2010-04-07 18:20:42 +00:00
Anton Korobeynikov a3e4989ad8 Correct VMVN itinerary: operand is read in the second cycle, not in the first.
llvm-svn: 100656
2010-04-07 18:20:36 +00:00
Anton Korobeynikov 140a65ce0b More A9 itineraries
llvm-svn: 100655
2010-04-07 18:20:29 +00:00
Anton Korobeynikov 1a1af5a830 Correct itinerary class for VPADD
llvm-svn: 100654
2010-04-07 18:20:24 +00:00
Anton Korobeynikov 4650fd5fc6 VP{MAX, MIN} are of IIC_VSUBi4D itin class as well.
llvm-svn: 100653
2010-04-07 18:20:18 +00:00
Anton Korobeynikov 7d4fad5942 VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.
llvm-svn: 100652
2010-04-07 18:20:13 +00:00
Johnny Chen c86256fa5d Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions.
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd).  The table is specified via
a list of vectors, which can be:

{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}

llvm-svn: 99789
2010-03-29 01:14:22 +00:00
Chris Lattner 3dad5fbeb9 fix integer negates to use the proper type for the zero vectors,
this also depends on the new "bitconvert dropping" behavior just
added to tblgen.

llvm-svn: 99757
2010-03-28 08:39:10 +00:00
Chris Lattner 6c223ee0e9 fix vnot matching to explicitly specify the type of the
input to be v8i8 or v16i8, which buildvectors get canonicalized to.

This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.

llvm-svn: 99754
2010-03-28 08:08:07 +00:00
Bob Wilson 0f8a02830a Fix indentation.
llvm-svn: 99705
2010-03-27 04:01:23 +00:00
Bob Wilson cf603fb1c5 Add a format argument to the N3V and N3VX classes, removing the N3Vf class.
llvm-svn: 99704
2010-03-27 03:56:52 +00:00
Johnny Chen 6094cdab9f Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set
it as the format for the appropriate N3V*SL*<> classes.  These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.

Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):

	vmlal.s32	q3, d2, d10[0]

llvm-svn: 99690
2010-03-27 01:03:13 +00:00
Johnny Chen 93acfbf441 Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified
to now take a format argument.  N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.

llvm-svn: 99676
2010-03-26 23:49:07 +00:00
Johnny Chen 0b57de3c4c Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.

Modify VEXTd and VEXTq classes to use the format.

llvm-svn: 99659
2010-03-26 22:28:56 +00:00
Johnny Chen 2cf04957c2 Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).

Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from.  N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.

Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.

llvm-svn: 99655
2010-03-26 21:26:28 +00:00
Johnny Chen 5d4e917d9f Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field.  The Vd, Vm fields are interpreted
the same between the two, though.

See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.

llvm-svn: 99590
2010-03-26 01:07:59 +00:00
Johnny Chen d82f9002e4 Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to
expect a Format arg.  N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.

llvm-svn: 99548
2010-03-25 20:39:04 +00:00
Johnny Chen 45ab3f3ccf Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,
instead of the current N2V.  Format of NVDupLane instances are set to NEONFrm
currently.

llvm-svn: 99518
2010-03-25 17:01:27 +00:00
Johnny Chen bff23ca690 Trivial formating change.
llvm-svn: 99428
2010-03-24 21:25:07 +00:00
Johnny Chen e99953ce9c Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
NVCVTFrm will later be used to describe "vcvt with fractional bits".

llvm-svn: 99415
2010-03-24 19:47:14 +00:00
Johnny Chen da44d5977f Reverted r99376. The disassembler will deal with the 2-reg format of these two
N3VX instructions using special case code.

llvm-svn: 99409
2010-03-24 18:46:34 +00:00
Johnny Chen aa9b1c81a7 Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
llvm-svn: 99376
2010-03-24 01:29:25 +00:00
Johnny Chen 9b1f60adec Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
respectively, and add some more comment.

llvm-svn: 99373
2010-03-24 00:57:50 +00:00
Johnny Chen 5be6d5a6a9 Add comment.
llvm-svn: 99327
2010-03-23 21:30:12 +00:00
Johnny Chen 5dbf39285d Add New NEON Format NVdVmVCVTFrm.
Converted some of the NEON vcvt instructions to this format.

llvm-svn: 99326
2010-03-23 21:25:38 +00:00
Bob Wilson 59f75bba24 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

llvm-svn: 99309
2010-03-23 18:54:46 +00:00
Bob Wilson 9b680e21c0 Rename some instructions to match the corresponding NEON opcode.
llvm-svn: 99266
2010-03-23 06:26:18 +00:00
Bob Wilson cc0a2a75a0 Change VST1 instructions for loading Q register values to operate on pairs
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265
2010-03-23 06:20:33 +00:00
Bob Wilson 340861d29e Change VLD1 instructions for loading Q register values to operate on pairs
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261
2010-03-23 05:25:43 +00:00
Bob Wilson e60e3ab624 Rename one more NEON instruction that I missed earlier.
llvm-svn: 99201
2010-03-22 20:31:39 +00:00
Bob Wilson c286c88db0 Regroup some instructions. No functional change.
llvm-svn: 99192
2010-03-22 18:22:06 +00:00
Bob Wilson c53a1125ff Rename some VLD1/VST1 instructions to match the implementation, i.e., the
corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189
2010-03-22 18:13:18 +00:00
Bob Wilson 98bf5189d7 Remove some redundant instruction classes.
llvm-svn: 99187
2010-03-22 18:02:38 +00:00
Bob Wilson debe0bdb13 Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
specify encoding bits in arguments instead of "let" expressions.

llvm-svn: 99185
2010-03-22 16:43:10 +00:00
Bob Wilson ae08a736d6 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095
2010-03-20 22:13:40 +00:00
Bob Wilson 59e5141d44 Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with
address register writeback.

llvm-svn: 99094
2010-03-20 21:57:36 +00:00
Bob Wilson b18adef4ad Add variants of VST2, VST3 and VST4 with address register writeback, and
rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.

llvm-svn: 99093
2010-03-20 21:45:18 +00:00
Bob Wilson 89ba42c4ce Add instructions for double-spaced VST3 and VST4 without address register
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99090
2010-03-20 21:15:48 +00:00
Bob Wilson 322cbff3d3 Add VST1 instructions with address register writeback.
llvm-svn: 99083
2010-03-20 20:54:36 +00:00
Bob Wilson 9152d96dfb Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with
address register writeback.

llvm-svn: 99082
2010-03-20 20:47:18 +00:00
Bob Wilson 9b1584245a Tidy some more comments and whitespace.
llvm-svn: 99081
2010-03-20 20:39:53 +00:00
Bob Wilson cf324658f6 Add variants of VLD2, VLD3 and VLD4 with address register writeback, and
rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.

llvm-svn: 99080
2010-03-20 20:10:51 +00:00
Bob Wilson 7ee900da22 Tidy some comments and whitespace for consistency.
llvm-svn: 99078
2010-03-20 19:57:03 +00:00
Bob Wilson c0795f8b87 Rename some instructions for consistency and sanity: use "_UPD" suffix for
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.

llvm-svn: 99066
2010-03-20 18:35:24 +00:00
Bob Wilson d092669b48 Add instructions for double-spaced VLD3 and VLD4 without address register
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99065
2010-03-20 18:14:26 +00:00
Bob Wilson 496766cb56 Add VLD1 instructions with address register writeback.
llvm-svn: 99062
2010-03-20 17:59:03 +00:00
Bob Wilson e4191e719b Revert this change, since it was causing ARM performance regressions.
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

llvm-svn: 99010
2010-03-19 22:51:32 +00:00
Anton Korobeynikov f11aa9e7b4 Get rid of target-specific fp <-> int nodes when still I'm here.
llvm-svn: 98889
2010-03-18 22:35:45 +00:00
Bob Wilson a7f236ae3a Refactor NEON ld/st instructions to hardcode class arguments that are constants.
No functional changes.

llvm-svn: 98860
2010-03-18 20:18:39 +00:00
Johnny Chen 274a0d3794 Revert 98745 with respect to the addition of NEONFrm subformats for disassembly.
There is a better way coming up.

llvm-svn: 98777
2010-03-17 23:26:50 +00:00
Johnny Chen 8f3004cff2 Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, ]

llvm-svn: 98745
2010-03-17 17:52:21 +00:00
Bob Wilson c7ba918b84 Revert 98683. It is breaking something in the disassembler.
llvm-svn: 98692
2010-03-16 23:01:13 +00:00
Bob Wilson c953bca10b Remove redundant writeback flag from ARM address mode 6. Also remove the
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.

llvm-svn: 98683
2010-03-16 21:44:40 +00:00
Bob Wilson 1b4e8cc69c --- Reverse-merging r98637 into '.':
U    test/CodeGen/ARM/tls2.ll
U    test/CodeGen/ARM/arm-negative-stride.ll
U    test/CodeGen/ARM/2009-10-30.ll
U    test/CodeGen/ARM/globals.ll
U    test/CodeGen/ARM/str_pre-2.ll
U    test/CodeGen/ARM/ldrd.ll
U    test/CodeGen/ARM/2009-10-27-double-align.ll
U    test/CodeGen/Thumb2/thumb2-strb.ll
U    test/CodeGen/Thumb2/ldr-str-imm12.ll
U    test/CodeGen/Thumb2/thumb2-strh.ll
U    test/CodeGen/Thumb2/thumb2-ldr.ll
U    test/CodeGen/Thumb2/thumb2-str_pre.ll
U    test/CodeGen/Thumb2/thumb2-str.ll
U    test/CodeGen/Thumb2/thumb2-ldrh.ll
U    utils/TableGen/TableGen.cpp
U    utils/TableGen/DisassemblerEmitter.cpp
D    utils/TableGen/RISCDisassemblerEmitter.h
D    utils/TableGen/RISCDisassemblerEmitter.cpp
U    Makefile.rules
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/Makefile
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D    lib/Target/ARM/Disassembler
U    lib/Target/ARM/ARMInstrFormats.td
U    lib/Target/ARM/ARMAddressingModes.h
U    lib/Target/ARM/Thumb2ITBlockPass.cpp

llvm-svn: 98640
2010-03-16 16:59:47 +00:00
Johnny Chen 3d9327bd06 Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, ]

llvm-svn: 98637
2010-03-16 16:36:54 +00:00
Chris Lattner ce81b3c120 fix an ambiguous pattern, contrary to expectations, scalar_to_vector
doesn't have a type constraint on the scalar because we don't have
an 'sAny' type.

llvm-svn: 98527
2010-03-15 00:52:43 +00:00
Bob Wilson 27cce1c0b6 Remove obsolete comments. VLDM is implemented in ARMInstrVFP.td.
llvm-svn: 98395
2010-03-12 22:00:08 +00:00
Chris Lattner b8a7427636 fix a bunch of partially ambiguous patterns on ARM. As an
example, this:

(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))

is ambiguous because DPR contains both f64 and v2f32.  tblgen
currently accidentally picks f64 because it's first in the 
regclass.

llvm-svn: 97955
2010-03-08 18:51:21 +00:00
Johnny Chen 86ba44a4c7 Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only.
A8.6.405

llvm-svn: 97052
2010-02-24 20:06:07 +00:00
Johnny Chen 03ac201ad9 Fixed typo of opcodestr, should be "vst1", not "vld1".
llvm-svn: 97044
2010-02-24 18:00:40 +00:00
Johnny Chen d5c472d811 Added for disassembly VST1 (multiple single elements) which stores elements to
memory from three or four registers and VST2 (multiple two-element structures)
which stores to memory from two double-spaced registers.

A8.6.391 & A8.6.393

llvm-svn: 97018
2010-02-24 02:57:20 +00:00
Johnny Chen b14a5c52bc Added for disassembly VLD1 (multiple single elements) which loads memory into
three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.

A8.6.307 & A8.6.310

llvm-svn: 96980
2010-02-23 20:51:23 +00:00
Johnny Chen 21dbd6f449 Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare to
(immediate ) for disassembly only.

A8.6.283, A8.6.285, A8.6.287, A8.6.290

llvm-svn: 96856
2010-02-23 01:42:58 +00:00
Johnny Chen 886915e3bb Added VCEQ (immediate ) NEON instruction for disassembly only.
A8.6.281

llvm-svn: 96838
2010-02-23 00:33:12 +00:00
Bob Wilson c6c13a3515 Use NEON vmin/vmax instructions for floating-point selects.
Radar 7461718.

llvm-svn: 96572
2010-02-18 06:05:53 +00:00
Bob Wilson cb2deb2aaf Remove the NEON N2VSInt instruction class: it's only used in one place and
since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.

llvm-svn: 96525
2010-02-17 22:42:54 +00:00
Bob Wilson 004d280d5e More cleanup for NEON:
* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.

llvm-svn: 96521
2010-02-17 22:23:11 +00:00
Bob Wilson 9e89907ed5 Wrap lines to 80 columns and generally try to clean up whitespace and
indentation.  No functional changes.

llvm-svn: 96418
2010-02-17 00:31:29 +00:00
Johnny Chen 1215c774f2 Add VBIF/VBIT for disassembly only.
A8.6.279

llvm-svn: 95713
2010-02-09 23:05:23 +00:00
Bob Wilson 7430a98619 Emit spaces after commas in Neon register lists. This is more consistent
with the rest of the assembly output, is easier to read, and matches the
expected output for gcc's Neon tests.

llvm-svn: 93703
2010-01-18 01:24:43 +00:00
Bob Wilson 9349437c65 The Neon "vtst" instruction takes a suffix that is the element size alone --
adding an "i" to the suffix, indicating that the elements are integers, is
accepted but not part of the standard syntax.  This helps us pass a few more
of the Neon tests from gcc.

llvm-svn: 93677
2010-01-17 06:35:17 +00:00
Johnny Chen 86fc920742 For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
llvm-svn: 90243
2009-12-01 17:37:06 +00:00
Johnny Chen ee536b0ea4 For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.
For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.

Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173
2009-12-01 00:02:02 +00:00
Evan Cheng 738a97a1db Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.

llvm-svn: 89706
2009-11-23 21:57:23 +00:00
Johnny Chen b6528d3244 Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup.  VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.

llvm-svn: 89699
2009-11-23 21:00:43 +00:00
Johnny Chen 5ad7416260 Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
{?,?,?,?} as op11_8 for VEXTd and VEXTq.

llvm-svn: 89693
2009-11-23 20:09:13 +00:00
Johnny Chen e97457afbc Partially revert r89377 by removing NLdStLN class definition from
ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.

llvm-svn: 89684
2009-11-23 18:16:16 +00:00
Johnny Chen ebc60ef80c Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane
should be left unspecified now that Bob Wilson has fixed pr5470.

llvm-svn: 89676
2009-11-23 17:48:17 +00:00
Evan Cheng a33fc86be3 Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
llvm-svn: 89542
2009-11-21 06:21:52 +00:00
Johnny Chen b3b8209d77 Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
fully specified at this level.  Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.

llvm-svn: 89377
2009-11-19 19:20:17 +00:00
Evan Cheng e129dd311e Use table to separate opcode from operands.
llvm-svn: 86965
2009-11-12 07:16:34 +00:00
Jim Grosbach d7cf55cd0e Use Unified Assembly Syntax for the ARM backend.
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
Bob Wilson d95ccd6c4d Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.

llvm-svn: 86301
2009-11-06 23:33:28 +00:00
Anton Korobeynikov 0f38d989bd Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
2009-11-02 00:11:39 +00:00
Jim Grosbach 5cba8de2c8 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
them for scalar floating point operations for now.

llvm-svn: 85697
2009-10-31 22:57:36 +00:00
Bob Wilson 0db964a3a0 Fix NEON VST2LN instruction encoding.
Patch by Johnny Chen.

llvm-svn: 84767
2009-10-21 17:54:01 +00:00
Bob Wilson 87671da29a Revert 84732. It was the wrong fix.
llvm-svn: 84766
2009-10-21 17:52:34 +00:00
Bob Wilson 5b5cb92816 Fix some more NEON instruction encoding problems.
Thanks to Johnny Chen for discovering the problem.

llvm-svn: 84732
2009-10-21 02:27:20 +00:00
Bob Wilson bd3650cc84 Leave some NEON instruction encoding bits unspecified instead of setting
a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.

llvm-svn: 84730
2009-10-21 02:15:46 +00:00
Jim Grosbach 772b2f84eb Refs: A8-598.
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.

Patch by Johnny Chen.

llvm-svn: 84572
2009-10-20 00:38:19 +00:00
Bob Wilson 01404ecec7 Fix more NEON instruction encodings.
Patch by Johnny Chen.

llvm-svn: 84243
2009-10-16 03:58:44 +00:00
Bob Wilson 4138b11c93 Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements.
Patch by Johnny Chen.

llvm-svn: 84206
2009-10-15 21:57:47 +00:00
Bob Wilson cfcf6bc70d Fix instruction encoding bits for NEON VPADAL.
Patch by Johnny Chen.

llvm-svn: 84146
2009-10-14 21:43:17 +00:00
Jim Grosbach 94068707e1 Inst{11-8} for vshl should be 0b0101, not 0b1111.
Refs: A7-17 & A8-750.

Patch by Johnny Chen.

llvm-svn: 84131
2009-10-14 20:31:01 +00:00
Bob Wilson 84e7967fae Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
llvm-svn: 83600
2009-10-09 00:01:36 +00:00
Bob Wilson c409030838 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
llvm-svn: 83598
2009-10-08 23:51:31 +00:00
Bob Wilson b851eb356a Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
llvm-svn: 83596
2009-10-08 23:38:24 +00:00
Bob Wilson 38ba47225a Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
2009-10-08 22:53:57 +00:00
Bob Wilson cf54e934f8 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
llvm-svn: 83585
2009-10-08 22:27:33 +00:00
Bob Wilson c2728f44a9 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
llvm-svn: 83568
2009-10-08 18:56:10 +00:00
Bob Wilson b6b0ab6117 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
llvm-svn: 83526
2009-10-08 05:18:18 +00:00
Bob Wilson 71387b4b2f Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
llvm-svn: 83518
2009-10-08 00:28:28 +00:00
Bob Wilson d4f5670096 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
llvm-svn: 83513
2009-10-08 00:21:01 +00:00
Bob Wilson 32cc4ec304 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
llvm-svn: 83508
2009-10-07 23:54:04 +00:00
Bob Wilson 5ef3c6d9f4 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
llvm-svn: 83506
2009-10-07 23:39:57 +00:00
Bob Wilson 763be1a248 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
llvm-svn: 83502
2009-10-07 22:57:01 +00:00
Bob Wilson 50820a2677 Add some instruction encoding bits for NEON load/store instructions.
llvm-svn: 83490
2009-10-07 21:53:04 +00:00
Bob Wilson e7ef4a9a6b Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
llvm-svn: 83486
2009-10-07 20:49:18 +00:00
Bob Wilson 23464866ad Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
llvm-svn: 83484
2009-10-07 20:30:08 +00:00
Bob Wilson 3dcb5377ef Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
llvm-svn: 83482
2009-10-07 18:47:39 +00:00
Bob Wilson ab3a9474d6 Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
llvm-svn: 83479
2009-10-07 18:09:32 +00:00
Bob Wilson 6bbefc2f67 Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
llvm-svn: 83471
2009-10-07 17:24:55 +00:00
Bob Wilson e6b778d5ff Add codegen support for NEON vld2 operations on quad registers.
llvm-svn: 83422
2009-10-06 22:01:59 +00:00
Bob Wilson d76b9b766c Add a comment to describe letters used in multiclass name suffixes.
llvm-svn: 83257
2009-10-03 04:44:16 +00:00
Bob Wilson a9abf57409 Fix encoding problem for VMLS instruction.
Thanks to Johnny Chen for pointing this out!

llvm-svn: 83256
2009-10-03 04:41:21 +00:00
Evan Cheng 1b2b64f618 Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
ld / st pairs, etc.

llvm-svn: 83197
2009-10-01 08:22:27 +00:00
David Goodwin bea6848f9d Finish scheduling itineraries for NEON.
llvm-svn: 82788
2009-09-25 18:38:29 +00:00
David Goodwin afcaf79603 Checkpoint NEON scheduling itineraries.
llvm-svn: 82657
2009-09-23 21:38:08 +00:00
Anton Korobeynikov 8d0fbebb9f Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to
constraint the register usage.

llvm-svn: 81635
2009-09-12 22:21:08 +00:00
Anton Korobeynikov 7697d37777 Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
llvm-svn: 81262
2009-09-08 22:51:43 +00:00
Anton Korobeynikov 59e2b8e894 Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
makes the code faster.

llvm-svn: 81220
2009-09-08 15:22:32 +00:00
Anton Korobeynikov f0da41c3e4 More missed vdup patterns
llvm-svn: 80838
2009-09-02 21:21:28 +00:00
Bob Wilson d7797754d4 Add support for generating code for vst{234}lane intrinsics.
llvm-svn: 80707
2009-09-01 18:51:56 +00:00
Bob Wilson da9817cddd Generate code for vld{234}_lane intrinsics.
llvm-svn: 80656
2009-09-01 04:26:28 +00:00
Anton Korobeynikov 3681144bd8 Add missed pattern
llvm-svn: 80502
2009-08-30 19:06:39 +00:00
Anton Korobeynikov cd41d07f29 Add missed extract_element pattern
llvm-svn: 80408
2009-08-28 23:41:26 +00:00
Anton Korobeynikov 076f105d86 Forgot about actual change :)
llvm-svn: 80250
2009-08-27 16:10:17 +00:00
Anton Korobeynikov 58ebae4acd Transform float scalar_to_vector into subreg accesses.
No idea whether this is profitable or not.

llvm-svn: 80245
2009-08-27 14:38:44 +00:00
Bob Wilson f1beef9f48 Remove some unused SDNode definitions.
llvm-svn: 80015
2009-08-25 17:52:39 +00:00
Bob Wilson 9129376719 Expose the instruction contraint string as an argument to the NLdSt class.
llvm-svn: 80011
2009-08-25 17:46:06 +00:00
Bob Wilson ceffeb6abd Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676
2009-08-21 21:58:55 +00:00
Anton Korobeynikov 232b19c3d5 Fix some typos and use type-based isel for VZIP/VUZP/VTRN
llvm-svn: 79625
2009-08-21 12:41:42 +00:00
Anton Korobeynikov ce3ff1be8a Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
llvm-svn: 79622
2009-08-21 12:40:50 +00:00
Anton Korobeynikov 38f284f2ae Provide vext.{16,32}
llvm-svn: 79620
2009-08-21 12:40:21 +00:00
Bob Wilson 32cd8550ce Add support for Neon VEXT (vector extract) shuffles.
This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.

llvm-svn: 79428
2009-08-19 17:03:43 +00:00
Bob Wilson eb54d51759 Create a new ARM-specific DAG node, VDUP, to represent a splat from a
scalar_to_vector.  Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.

llvm-svn: 78994
2009-08-14 05:13:08 +00:00
Bob Wilson cce31f6831 During legalization, change Neon vdup_lane operations from shuffles to
target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993
2009-08-14 05:08:32 +00:00
Bob Wilson ef6e602bf4 Revert r78852 for now. I want to do this differently, but I don't have time
to fix it tonight.

llvm-svn: 78896
2009-08-13 05:58:56 +00:00
Bob Wilson ff2db10211 Recognize Neon VDUP shuffles during legalization instead of selection.
llvm-svn: 78852
2009-08-12 22:54:19 +00:00
Bob Wilson ea3a402ae7 Recognize Neon VREV shuffles during legalization instead of selection.
llvm-svn: 78850
2009-08-12 22:31:50 +00:00
Bob Wilson 4b35448360 Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
llvm-svn: 78835
2009-08-12 20:51:55 +00:00