Commit Graph

50 Commits

Author SHA1 Message Date
Brendon Cahoon 7c8a3b0ef6 [Hexagon] Generate hardware loop for a vectorized loop
The induction variable in the vectorized loop wasn't
recognized properly, so a hardware loop wasn't generated.

Differential Revision: http://reviews.llvm.org/D9722

llvm-svn: 237388
2015-05-14 20:36:19 +00:00
Brendon Cahoon 485bea74ad [Hexagon] Remove dead constant assignment in hardware loop pass
After converting a loop to a hardware loop, the pass should remove
any unnecessary instructions from the old compare-and-branch
code. This patch removes a dead constant assignment that was
used in the compare instruction.

Differential Revision: http://reviews.llvm.org/D9720

llvm-svn: 237373
2015-05-14 17:31:40 +00:00
Brendon Cahoon 9376e9998e [Hexagon] Check for underflow/wrap in hardware loop pass
If the loop trip count may underflow or wrap, the compiler should
not generate a hardware loop since the trip count will be
incorrect.

llvm-svn: 237365
2015-05-14 14:15:08 +00:00
Brendon Cahoon d11c92a41c [Hexagon] Generate loop1 instruction for nested loops
loop1 is for the outer loop and loop0 is for the inner loop.

Differential Revision: http://reviews.llvm.org/D9680

llvm-svn: 237266
2015-05-13 17:56:03 +00:00
Brendon Cahoon 254e656862 [Hexagon] Generate hardware loop when loop has a critical edge
The hardware loop pass should try to generate a hardware loop
instruction when the original loop has a critical edge.

Differential Revision: http://reviews.llvm.org/D9678

llvm-svn: 237258
2015-05-13 14:54:24 +00:00
Brendon Cahoon bece8edcdd [Hexagon] Generate more hardware loops
Refactored parts of the hardware loop pass to generate
more. Also, added more tests.

Differential Revision: http://reviews.llvm.org/D9568

llvm-svn: 236896
2015-05-08 20:18:21 +00:00
Brendon Cahoon df43e68629 [Hexagon] Update AnalyzeBranch, etc target hooks
Improved the AnalyzeBranch, InsertBranch, and RemoveBranch
functions in order to handle more of our branch instructions.
This requires changes to analyzeCompare and PredicateInstructions.
Specifically, we've added support for new value compare jumps,
improved handling of endloop, added more compare instructions,
and improved support for predicate instructions.

Differential Revision: http://reviews.llvm.org/D9559

llvm-svn: 236876
2015-05-08 16:16:29 +00:00
Benjamin Kramer 7bd1f7cb58 Remove the remaining uses of abs64 and nuke it.
std::abs works just fine and we're already using it in many places. NFC intended.

llvm-svn: 231696
2015-03-09 20:20:16 +00:00
Colin LeMahieu 27d50073b3 [Hexagon] Renaming A2_subri, A2_andir, A2_orir. Fixing formatting.
llvm-svn: 228326
2015-02-05 18:38:08 +00:00
Colin LeMahieu f297dbed48 [Hexagon] Renaming A2_addi and formatting.
llvm-svn: 228318
2015-02-05 17:49:13 +00:00
Eric Christopher 2c44f43ebe Remove unused class variables and update calls to get the subtarget
off of the machine function.

llvm-svn: 227837
2015-02-02 19:05:28 +00:00
Colin LeMahieu c91fabc233 [Hexagon] Removing old versions of cmph and updating references.
llvm-svn: 226013
2015-01-14 18:26:14 +00:00
Colin LeMahieu fa947906bf [Hexagon] Deleting versions of compare-not that don't have encoding information. Updating references.
llvm-svn: 226003
2015-01-14 16:49:12 +00:00
Colin LeMahieu 0f850bde0e [Hexagon] Removing old variants of instructions and updating references.
llvm-svn: 224612
2014-12-19 20:29:29 +00:00
Colin LeMahieu 5ccbb1298b [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
llvm-svn: 224556
2014-12-19 00:06:53 +00:00
Colin LeMahieu 174476ed96 Reverting 224550, was not ready for commit.
llvm-svn: 224552
2014-12-18 23:36:15 +00:00
Colin LeMahieu 9000481cda [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
llvm-svn: 224550
2014-12-18 23:27:51 +00:00
Colin LeMahieu aa1bade7b4 [Hexagon] Updating doubleword shift usages to new versions.
llvm-svn: 224391
2014-12-16 23:36:15 +00:00
Colin LeMahieu db0b13cef0 [Hexagon] Adding encodings for JR class instructions. Updating complier usages.
llvm-svn: 223967
2014-12-10 21:24:10 +00:00
Colin LeMahieu 4af437fee5 [Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.
llvm-svn: 223821
2014-12-09 20:23:30 +00:00
Colin LeMahieu 6e0f9f8d61 [Hexagon] Adding cmp* immediate form instructions.
llvm-svn: 222849
2014-11-26 19:43:12 +00:00
Colin LeMahieu 902157c249 [Hexagon] Replacing cmp* instructions with ones that contain encoding bits.
llvm-svn: 222771
2014-11-25 18:20:52 +00:00
Colin LeMahieu e88447d8de [Hexagon] Removing SUB_rr and replacing with A2_sub.
llvm-svn: 222571
2014-11-21 21:19:18 +00:00
Sid Manning 67a8936a84 Minor spelling correction.
Reviewers: adasgupt, jverma, sidneym

Differential Revision: http://reviews.llvm.org/D5025

llvm-svn: 216667
2014-08-28 14:16:32 +00:00
Eric Christopher d913448b38 Remove the TargetMachine forwards for TargetSubtargetInfo based
information and update all callers. No functional change.

llvm-svn: 214781
2014-08-04 21:25:23 +00:00
Craig Topper 906c2cd2e6 [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition
llvm-svn: 207508
2014-04-29 07:58:16 +00:00
Craig Topper 062a2baef0 [C++] Use 'nullptr'. Target edition.
llvm-svn: 207197
2014-04-25 05:30:21 +00:00
Chandler Carruth 84e68b2994 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
definition below all of the header #include lines, lib/Target/...
edition.

llvm-svn: 206842
2014-04-22 02:41:26 +00:00
Owen Anderson 16c6bf49b7 Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing
operator* on the by-operand iterators to return a MachineOperand& rather than
a MachineInstr&.  At this point they almost behave like normal iterators!

Again, this requires making some existing loops more verbose, but should pave
the way for the big range-based for-loop cleanups in the future.

llvm-svn: 203865
2014-03-13 23:12:04 +00:00
Benjamin Kramer b6d0bd48bd [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
Remove the old functions.

llvm-svn: 202636
2014-03-02 12:27:27 +00:00
Alp Toker cb40291100 Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

llvm-svn: 200018
2014-01-24 17:20:08 +00:00
Chandler Carruth 8a8cd2bab9 Re-sort all of the includes with ./utils/sort_includes.py so that
subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.

Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.

llvm-svn: 198685
2014-01-07 11:48:04 +00:00
Benjamin Kramer 7d6052687e Replace some unnecessary vector copies with references.
llvm-svn: 190770
2013-09-15 22:04:42 +00:00
Craig Topper b94011fd28 Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
llvm-svn: 186274
2013-07-14 04:42:23 +00:00
Jyotsna Verma 5ed5181178 Hexagon: Use multiclass for Jump instructions.
llvm-svn: 180885
2013-05-01 21:37:34 +00:00
Jyotsna Verma 89c84821ea Hexagon: Remove assembler mapped instruction definitions.
llvm-svn: 180133
2013-04-23 19:15:55 +00:00
Duncan Sands fee96f832d Remove unused typedef.
llvm-svn: 178462
2013-04-01 13:46:15 +00:00
Tim Northover d3490dc06a Switch to LLVM support function abs64 to keep VS2008 happy.
llvm-svn: 178141
2013-03-27 13:15:08 +00:00
Krzysztof Parzyszek 9a278f108a Extend Hexagon hardware loop generation to handle various additional cases:
- variety of compare instructions,
- loops with no preheader,
- arbitrary lower and upper bounds.

llvm-svn: 174904
2013-02-11 21:37:55 +00:00
Chandler Carruth 9fb823bbd4 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

llvm-svn: 171366
2013-01-02 11:36:10 +00:00
Matthew Curtis 7a93811e8b In hexagon convertToHardwareLoop, don't deref end() iterator
In particular, check if MachineBasicBlock::iterator is end() before
using it to call getDebugLoc();

See also this thread on llvm-commits:
   http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/155914.html

llvm-svn: 169634
2012-12-07 21:03:15 +00:00
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Jakob Stoklund Olesen 978c1280a5 Don't use getNextOperandForReg().
This way of using getNextOperandForReg() was unlikely to work as
intended. We don't give any guarantees about the order of operands in
the use-def chains, so looking only at operands following a given
operand in the chain doesn't make sense.

llvm-svn: 161542
2012-08-08 23:44:04 +00:00
Benjamin Kramer bde9176663 Fix typos found by http://github.com/lyda/misspell-check
llvm-svn: 157885
2012-06-02 10:20:22 +00:00
Craig Topper c7242e054d Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
llvm-svn: 155188
2012-04-20 07:30:17 +00:00
Craig Topper b25fda95f6 Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
llvm-svn: 152997
2012-03-17 18:46:09 +00:00
Sirish Pande 30804c24ca Optimize redundant sign extends and negation of predicates.
llvm-svn: 150606
2012-02-15 18:52:27 +00:00
Eric Christopher d9811eb7be Revert "Optimize redundant sign extends and negation of predicates"
as it's breaking the build.

This reverts commit 11241abca5e2a313412fed594bb9d9fa2a2057fb.

llvm-svn: 150604
2012-02-15 18:32:25 +00:00
Sirish Pande 4736aee81e Optimize redundant sign extends and negation of predicates
llvm-svn: 150601
2012-02-15 18:22:18 +00:00
Tony Linthicum 1213a7a57f Hexagon backend support
llvm-svn: 146412
2011-12-12 21:14:40 +00:00