Evan Cheng
082c8785ef
Handle BUILD_VECTOR with all zero elements.
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llvm-svn: 27056
2006-03-24 07:29:27 +00:00
Evan Cheng
2595a687da
More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd.
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llvm-svn: 27040
2006-03-24 02:58:06 +00:00
Evan Cheng
d27fb3e85e
Handle more shuffle cases with SHUFP* instructions.
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llvm-svn: 27024
2006-03-24 01:18:28 +00:00
Evan Cheng
021bb7c956
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
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64-bit vector shuffle.
llvm-svn: 26964
2006-03-22 22:07:06 +00:00
Evan Cheng
68ad48bd1a
- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
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splat and PSHUFD cases.
- Clean up shuffle / splat matching code.
llvm-svn: 26954
2006-03-22 18:59:22 +00:00
Evan Cheng
8fdbdf20cd
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
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PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
llvm-svn: 26951
2006-03-22 08:01:21 +00:00
Evan Cheng
d097e67544
Some splat and shuffle support.
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llvm-svn: 26940
2006-03-22 02:53:00 +00:00
Evan Cheng
d5e905d762
- Use movaps to store 128-bit vector integers.
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- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
llvm-svn: 26932
2006-03-21 23:01:21 +00:00
Evan Cheng
2dd2c652b2
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
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llvm-svn: 26742
2006-03-13 23:20:37 +00:00
Evan Cheng
e0ed6ec13f
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
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and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
llvm-svn: 26335
2006-02-23 20:41:18 +00:00
Evan Cheng
1f342c2884
PIC related bug fixes.
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1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
llvm-svn: 26324
2006-02-23 02:43:52 +00:00
Chris Lattner
7ad77dfc2a
split register class handling from explicit physreg handling.
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llvm-svn: 26308
2006-02-22 00:56:39 +00:00
Chris Lattner
7bb4696dc3
Updates to match change of getRegForInlineAsmConstraint prototype
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llvm-svn: 26305
2006-02-21 23:11:00 +00:00
Evan Cheng
5588de9415
x86 / Darwin PIC support.
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llvm-svn: 26273
2006-02-18 00:15:05 +00:00
Nate Begeman
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
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and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
Nate Begeman
8a77efe4f7
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
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and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
Evan Cheng
11613a5219
Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
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flag so it can be flagged to a FST.
llvm-svn: 25953
2006-02-04 02:20:30 +00:00
Evan Cheng
72d5c256c9
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
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- Use XORP* to implement fneg.
llvm-svn: 25857
2006-01-31 22:28:30 +00:00
Chris Lattner
c642aa5e1c
* Fix 80-column violations
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* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
llvm-svn: 25854
2006-01-31 19:43:35 +00:00
Evan Cheng
2dd217b88f
Added custom lowering of fabs
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llvm-svn: 25831
2006-01-31 03:14:29 +00:00
Evan Cheng
5b97fcf0f5
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
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conversions. SSE does not have instructions to handle these tasks.
llvm-svn: 25817
2006-01-30 08:02:57 +00:00
Chris Lattner
f0b24d2dc0
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
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llvm-svn: 25803
2006-01-30 04:09:27 +00:00
Chris Lattner
c6fa0282d2
adjust prototype
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llvm-svn: 25798
2006-01-30 03:49:07 +00:00
Nate Begeman
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
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the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
Evan Cheng
cde9e30bc6
x86 CPU detection and proper subtarget support
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llvm-svn: 25679
2006-01-27 08:10:46 +00:00
Nate Begeman
e74795cd70
First part of bug 680:
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Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
Evan Cheng
6305e50ee1
Fix sint_to_fp (fild*) support.
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llvm-svn: 25257
2006-01-12 22:54:21 +00:00
Evan Cheng
ae986f1f1e
Support for MEMCPY and MEMSET.
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llvm-svn: 25226
2006-01-11 22:15:48 +00:00
Evan Cheng
339edad775
SSE cmov support.
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llvm-svn: 25190
2006-01-11 00:33:36 +00:00
Evan Cheng
9c249c37f8
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
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llvm-svn: 25158
2006-01-09 18:33:28 +00:00
Evan Cheng
172fce7050
* Fast call support.
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* FP cmp, setcc, etc.
llvm-svn: 25117
2006-01-06 00:43:03 +00:00
Evan Cheng
45e19098a6
DAG based isel call support.
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llvm-svn: 25103
2006-01-05 00:27:02 +00:00
Evan Cheng
5c59d49630
More X86 floating point patterns.
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llvm-svn: 24990
2005-12-23 07:31:11 +00:00
Evan Cheng
9cdc16c6d3
* Fix a GlobalAddress lowering bug.
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* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
llvm-svn: 24921
2005-12-21 23:05:39 +00:00
Evan Cheng
c1583dbd63
* Added support for X86 RET with an additional operand to specify number of
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bytes to pop off stack.
* Added support for X86 SETCC.
llvm-svn: 24917
2005-12-21 20:21:51 +00:00
Evan Cheng
a74ce62746
* Added lowering hook for external weak global address. It inserts a load
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for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
llvm-svn: 24888
2005-12-21 02:39:21 +00:00
Evan Cheng
6af02635a7
Added a hook to print out names of target specific DAG nodes.
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llvm-svn: 24877
2005-12-20 06:22:03 +00:00
Evan Cheng
6fc31046aa
X86 conditional branch support.
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llvm-svn: 24870
2005-12-19 23:12:38 +00:00
Evan Cheng
225a4d0d6d
X86 lowers SELECT to a cmp / test followed by a conditional move.
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llvm-svn: 24754
2005-12-17 01:21:05 +00:00
Andrew Lenharth
0bf68ae434
The second patch of X86 support for read cycle counter.
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llvm-svn: 24430
2005-11-20 21:41:10 +00:00
Chris Lattner
76ac068568
Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch
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contributed by Evan Cheng.
llvm-svn: 24358
2005-11-15 00:40:23 +00:00