d5edb3847a
Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts.
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Patch by Jack Carter.
llvm-svn: 144139
2011-11-08 22:26:47 +00:00
82cd9e81fc
Added invariant field to the DAG.getLoad method and changed all calls.
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When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
llvm-svn: 144100
2011-11-08 18:42:53 +00:00
71133fe9c6
This patch handles unaligned loads and stores in Mips JIT. Mips backend
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implements unaligned loads and stores with assembler macro-instructions
ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions
instead of these macros. Since each unaligned load/store is expanded
into two corresponding loads/stores where offset for second load/store is
modified by +3 (for words) or +1 (for halfwords).
Patch by Petar Jovanovic and Sasa Stankovic.
llvm-svn: 144081
2011-11-08 12:47:11 +00:00
2216f73676
Various Mips64 floating point instruction patterns.
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llvm-svn: 144019
2011-11-07 21:38:58 +00:00
b2d37760a2
Add definition of the base class for floating point comparison instructions
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and add Mips64's version too.
llvm-svn: 144018
2011-11-07 21:37:33 +00:00
81c14002dc
Add code needed for copying between 64-bit integer and floating pointer
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registers.
llvm-svn: 144017
2011-11-07 21:35:45 +00:00
1537e297e1
Add definitions of 64-bit instructions which move data between integer and
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floating pointer registers.
llvm-svn: 144016
2011-11-07 21:32:58 +00:00
2b8d1f163f
Add definition of 64-bit load upper immediate.
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llvm-svn: 143994
2011-11-07 19:10:49 +00:00
2f4480046b
Include RegSaveAreaSize in the computation of stack size.
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llvm-svn: 143993
2011-11-07 19:07:35 +00:00
7bcecd486f
Define functions that get or set the size of area on callee's stack frame which
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is used to save va_arg or byval arguments passed in registers.
llvm-svn: 143992
2011-11-07 19:06:10 +00:00
d9c2e46cfb
Use array_lengthof to compute the number of iterations of a loop.
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llvm-svn: 143991
2011-11-07 19:03:40 +00:00
cf7e5b0976
Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted
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when shift amount is larger than 32.
llvm-svn: 143990
2011-11-07 19:01:49 +00:00
770f0646db
Make the type of shift amount i32 in order to reduce the number of shift
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instruction definitions.
llvm-svn: 143989
2011-11-07 18:59:49 +00:00
d5c1329078
Add 64-bit to 32-bit trunc pattern.
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llvm-svn: 143988
2011-11-07 18:57:41 +00:00
20baffb257
Replace (Lower|Upper)caseString in favor of StringRef's newest methods.
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llvm-svn: 143891
2011-11-06 20:37:06 +00:00
4a9c6426ff
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just
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added a layer of indirection with no value (not even conciseness).
llvm-svn: 143727
2011-11-04 19:04:23 +00:00
bf9bba47a1
build: Add initial cut at LLVMBuild.txt files.
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llvm-svn: 143634
2011-11-03 18:53:17 +00:00
104b7e3f2c
Make changes necessary in LowerFormalArguments to support Mips64.
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llvm-svn: 143218
2011-10-28 19:55:48 +00:00
b20a325baf
Make changes necessary in LowerCall to support Mips64.
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llvm-svn: 143217
2011-10-28 19:49:00 +00:00
7989f15d37
Add variable IsO32 to MipsTargetLowering.
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llvm-svn: 143213
2011-10-28 18:47:24 +00:00
c0ecd1f7ed
Corrects previously incorrect $sp change in MipsCompilationCallback.
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The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned
Patch by Petar Jovanovic.
llvm-svn: 142930
2011-10-25 17:30:47 +00:00
2312a3aaa0
Final patch that completes old JIT support for Mips:
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-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
llvm-svn: 142378
2011-10-18 17:50:36 +00:00
2b7a1ff77f
Coding style cleanups. No functionality change.
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llvm-svn: 142341
2011-10-18 07:40:22 +00:00
4c42be5b32
Fix misc warnings. Patch by Joe Abbey.
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llvm-svn: 142332
2011-10-18 03:17:34 +00:00
a7e0b90897
Add definitions of conditional moves with 64-bit operands. Comment out code for
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expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
llvm-svn: 142226
2011-10-17 18:53:29 +00:00
975bfc9b45
Move class and instruction definitions for conditional moves to a seperate file.
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llvm-svn: 142220
2011-10-17 18:43:19 +00:00
3634f34659
Revert change made in r142205.
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llvm-svn: 142217
2011-10-17 18:33:24 +00:00
33fe8f908c
Redefine count-leading 0s and 1s instructions.
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llvm-svn: 142216
2011-10-17 18:26:37 +00:00
8c446be204
Redefine mfhi/lo and mthi/lo instructions.
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llvm-svn: 142214
2011-10-17 18:24:15 +00:00
0317b65367
Redefine multiply and divide instructions.
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llvm-svn: 142211
2011-10-17 18:21:24 +00:00
2736bbc09e
Add definition of a base class for logical shift/rotate instructions with two
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source registers and redefine 32-bit and 64-bit instructions.
llvm-svn: 142210
2011-10-17 18:17:58 +00:00
73081309c3
Add definition of a base class for logical shift/rotate immediate instructions
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and have 32-bit and 64-bit instructions derive from it.
llvm-svn: 142207
2011-10-17 18:06:56 +00:00
e3f27b79dc
Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
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llvm-svn: 142205
2011-10-17 18:01:00 +00:00
44419bfd54
Add f128 to datalayout string.
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llvm-svn: 141978
2011-10-14 19:14:50 +00:00
62b34a65f9
Revert r141932, r141936 and r141937.
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llvm-svn: 141959
2011-10-14 17:16:39 +00:00
d9ea7c8c31
Definition of function getMipsRegisterNumbering.
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Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141938
2011-10-14 03:04:24 +00:00
1742a2c093
Add definition of class MipsELFWriterInfo.
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Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141937
2011-10-14 02:55:47 +00:00
0fc7d7af5a
Add missing relocation types.
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Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141936
2011-10-14 02:47:50 +00:00
769fc971b4
Fixup enumerations.
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Patch by Jack Carter at Mips.
llvm-svn: 141934
2011-10-14 02:38:56 +00:00
4e2bfe0770
Add more Mips relocation types.
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Patch by Jack Carter at Mips.
llvm-svn: 141932
2011-10-14 02:17:30 +00:00
3261c0fa6e
Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
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llvm-svn: 141761
2011-10-12 01:05:13 +00:00
c57febff4a
Fix encoding of 32-bit integer instructions. Change names of operands and nodes.
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Remove unused classes.
llvm-svn: 141757
2011-10-12 00:56:06 +00:00
0f4ecf7548
Change name of class to ArithOverflowR.
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llvm-svn: 141743
2011-10-11 23:43:48 +00:00
8f0d549c4c
Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
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instructions with two register operands derive from it.
llvm-svn: 141742
2011-10-11 23:38:52 +00:00
8d4f74a6b1
Fix comment.
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llvm-svn: 141737
2011-10-11 23:12:12 +00:00
ae5a9d6578
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
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arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
llvm-svn: 141736
2011-10-11 23:05:46 +00:00
1c18465859
Fix function isUnalignedLoadStore.
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llvm-svn: 141722
2011-10-11 22:04:01 +00:00
10ae11fd57
Remove unused PatLeaf.
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llvm-svn: 141720
2011-10-11 21:53:08 +00:00
453ac88b56
Change the names of 64-bit logical instructions so that they match the names of
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the real instructions.
llvm-svn: 141718
2011-10-11 21:48:01 +00:00
46a7994ac9
Remove redundancy in setcc patterns using multiclass.
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llvm-svn: 141715
2011-10-11 21:40:01 +00:00
Bruno Cardoso Lopes