maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
10,818 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

57 Commits

Author SHA1 Message Date
Alkis Evlogimenos ea81b79a97 A big X86 instruction rename. The instructions are renamed to make 
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995
 2004-02-29 08:50:03 +00:00
Alkis Evlogimenos 876f6f96d0 Use correct template for ADC instruction with memory operands. 
llvm-svn: 11974
 2004-02-29 02:18:17 +00:00
Alkis Evlogimenos fa63580517 SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them 
to denote this fact.

llvm-svn: 11972
 2004-02-28 23:46:44 +00:00
Alkis Evlogimenos 4953ae085a Floating point loads/stores act on memory operands. Rename them to 
denote this fact.

llvm-svn: 11971
 2004-02-28 23:42:35 +00:00
Alkis Evlogimenos c6948fa762 Rename instruction templates to be easier to the human eye to 
parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970
 2004-02-28 23:09:03 +00:00
Alkis Evlogimenos 194939086d Each instruction now has both an ImmType and a MemType. This describes 
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967
 2004-02-28 22:02:05 +00:00
Alkis Evlogimenos 2debead504 Do not generate instructions with mismatched memory/immediate sized 
operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944
 2004-02-28 06:01:43 +00:00
Alkis Evlogimenos 24b3d0bdae Further comment updates. 
llvm-svn: 11933
 2004-02-28 03:20:31 +00:00
Alkis Evlogimenos f87966b8c4 Update comments. 
llvm-svn: 11932
 2004-02-28 03:12:31 +00:00
Alkis Evlogimenos 2dbc79df84 My previous commit broke the jit. The shift instructions always take 
an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931
 2004-02-28 02:56:26 +00:00
Alkis Evlogimenos b10b04c5ec Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of 
instructions.

llvm-svn: 11923
 2004-02-27 19:46:30 +00:00
Alkis Evlogimenos 75ed0f67bf Fix encoding of ADD and SUB family of instructions. Also rearrange 
them so that they are consistent with AND, XOR, etc...

llvm-svn: 11922
 2004-02-27 18:57:00 +00:00
Alkis Evlogimenos 58270fcf1f Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}. 
llvm-svn: 11921
 2004-02-27 18:55:12 +00:00
Alkis Evlogimenos 9476b7cbe5 Add memory operand folding support for the SETcc family of 
instructions.

llvm-svn: 11907
 2004-02-27 16:13:37 +00:00
Alkis Evlogimenos 8d99063b38 Add memory operand folding support for SHLD and SHRD instructions. 
llvm-svn: 11905
 2004-02-27 15:03:18 +00:00
Alkis Evlogimenos 3537404299 Add memory operand folding support for SHL, SHR and SAR, SHLD instructions. 
llvm-svn: 11903
 2004-02-27 09:28:43 +00:00
Alkis Evlogimenos f020dfb43c Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them 
consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902
 2004-02-27 06:57:05 +00:00
Chris Lattner 378157c3d7 Add a new cmove instruction 
llvm-svn: 11722
 2004-02-23 01:16:05 +00:00
Alkis Evlogimenos 6401b22fc2 Fix argument size for MOVSX and MOVZX instructions. 
llvm-svn: 11576
 2004-02-18 16:20:40 +00:00
Alkis Evlogimenos 47ea17a852 These store to memory too. 
llvm-svn: 11558
 2004-02-17 17:53:48 +00:00
Chris Lattner 49794be442 These store to memory, not read from it. 
llvm-svn: 11556
 2004-02-17 17:46:50 +00:00
Alkis Evlogimenos 546513ccfd Add TEST and XCHG memory operand support. 
llvm-svn: 11550
 2004-02-17 15:48:42 +00:00
Alkis Evlogimenos f08064b714 Add OR and XOR memory operand support. 
llvm-svn: 11549
 2004-02-17 15:33:14 +00:00
Alkis Evlogimenos e5585328d8 Add memory operand folding support for MUL, DIV, IDIV, NEG, NOT, 
MOVSX, and MOVZX.

llvm-svn: 11546
 2004-02-17 09:14:23 +00:00
Alkis Evlogimenos 574c7c9ce9 Add CMP{rm,mr,mi}{8,16,32}, INCm{8,16,32} and DECm{8,16,32} instructions. 
llvm-svn: 11544
 2004-02-17 08:49:00 +00:00
Alkis Evlogimenos d5ce14ddd1 Add SUB{rm,mr,mi}{8,16,32} instructions. 
llvm-svn: 11543
 2004-02-17 08:17:40 +00:00
Alkis Evlogimenos b591e5de31 Add support for ADC{rm.mr}32 and SBB{rm,mr}32. 
llvm-svn: 11540
 2004-02-17 08:06:31 +00:00
Chris Lattner 3abcdf3b90 Fix the mneumonics for the mov instructions to have the source and destination 
order in the correct sense!! Arg!

llvm-svn: 11530
 2004-02-17 06:28:19 +00:00
Chris Lattner ebd90733b0 Fix the last crimes against nature that used the 'ir' ordering to use the 
'ri' ordering instead... no it's not possible to store a register into an
immediate!

llvm-svn: 11529
 2004-02-17 06:24:02 +00:00
Chris Lattner 288e043e1b Rename MOVi[mr] instructions to MOV[rm]i 
llvm-svn: 11527
 2004-02-17 06:16:44 +00:00
Chris Lattner c9586411cf Add mem forms of AND instructions 
llvm-svn: 11521
 2004-02-17 05:25:50 +00:00
Chris Lattner 818bcec247 Rename the IMULri* instructions to IMULrri, as they are actually three address 
instructions.  Add forms of these instructions that read from memory

llvm-svn: 11518
 2004-02-17 04:26:43 +00:00
Alkis Evlogimenos f6ce2e313a Add two more variants of add. Update comments. 
llvm-svn: 11510
 2004-02-16 23:48:42 +00:00
Chris Lattner 544c9781db Add some ADD instructions that take memory operands for Alkis 
llvm-svn: 11502
 2004-02-16 18:19:31 +00:00
Chris Lattner 2e4acc0a73 Add support for the 'pop' instruction 
llvm-svn: 11451
 2004-02-14 21:06:02 +00:00
Chris Lattner d6a39eaa70 Urg, right. These need an input value... 
llvm-svn: 11443
 2004-02-14 04:47:23 +00:00
Chris Lattner 8bed37595d add 'rep stos[bwd]' instructions 
llvm-svn: 11441
 2004-02-14 04:45:37 +00:00
Chris Lattner 8dc99feeaf Add support for the rep movs[bwd] instructions, and emit them when code 
generating the llvm.memcpy intrinsic.

llvm-svn: 11351
 2004-02-12 17:53:22 +00:00
Alkis Evlogimenos dbf4b42fde IMULri* instructions do not require their first two registers operands 
to be the same (IOW they are not two address instructions).

llvm-svn: 11117
 2004-02-04 17:21:04 +00:00
Chris Lattner 3c8c72c54f Add the ftst instruction 
llvm-svn: 11095
 2004-02-03 07:27:50 +00:00
Chris Lattner 63b61e8739 No need to declare implicit uses/defs of ST0 
llvm-svn: 11081
 2004-02-02 19:57:45 +00:00
Chris Lattner 30d26ac561 Generate the fchs instruction to negate a floating point number 
llvm-svn: 11078
 2004-02-02 19:31:38 +00:00
Alkis Evlogimenos 68cff6bf4d Remove floating point killer pass. This is now implemented in the 
instruction selector by adding a new pseudo-instruction
FP_REG_KILL. This instruction implicitly defines all x86 fp registers
and is a terminator so that passes which add machine code at the end
of basic blocks (like phi elimination) do not add instructions between
it and the branch or return instruction.

llvm-svn: 10562
 2003-12-20 16:22:59 +00:00
John Criswell 29265fe981 Added LLVM copyright header. 
llvm-svn: 9321
 2003-10-21 15:17:13 +00:00
Chris Lattner 6acb1bedb1 Emit x86 instructions for: A = B op C, where A and B are 16-bit registers, 
C is a constant which can be sign-extended from 8 bits without value loss,
and op is one of: add, sub, imul, and, or, xor.

This allows the JIT to emit the one byte version of the constant instead of
the two or 4 byte version.  Because these instructions are very common, this
can save a LOT of code space.  For example, I sampled two benchmarks, 176.gcc
and 254.gap.

BM        Old     New    Reduction
176.gcc 2673621 2548962  4.89%
254.gap  498261  475104  4.87%

Note that while the percentage is not spectacular, this did eliminate
124.6 _KILOBYTES_ of codespace from gcc.  Not bad.

Note that this doesn't effect the llc version at all, because the assembler
already does this optimization.

llvm-svn: 9284
 2003-10-20 05:53:31 +00:00
Chris Lattner 97e1b55723 * Rename X86::IMULr16 -> X86::IMULrr16 
* Implement R1 = R2 * C where R1 and R2 are 32 or 16 bits. This avoids an
  extra copy into a register, reducing register pressure.

llvm-svn: 9278
 2003-10-20 03:42:58 +00:00
Chris Lattner 55a8ef0cc8 Add some new instructions. Wheee 
llvm-svn: 9266
 2003-10-19 19:25:35 +00:00
Chris Lattner 7235d86507 Add support for unconditional branches and for emitting JE instructions 
llvm-svn: 7872
 2003-08-15 04:50:49 +00:00
Chris Lattner 7606fa0d41 Add basic support for 16 and 32 bit function arguments! 
llvm-svn: 7755
 2003-08-11 21:30:00 +00:00
Chris Lattner 2923637f63 Add (ret int) expander so that we can at least write testcases 
llvm-svn: 7730
 2003-08-11 15:48:00 +00:00