6192b6570d
ARM assembly aliases for BIC<-->AND (immediate).
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When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
llvm-svn: 146283
2011-12-09 22:02:17 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
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Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
7e0a793183
Handle reloc_signed_4byte in here. Not doing so was a regression from my
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previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.
llvm-svn: 146273
2011-12-09 19:57:29 +00:00
e7739d484f
The second part of support for generating dwarf for assembly source files. This
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generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.
The next part will be to get the clang driver to enable this when assembling
a .s file. rdar://9275556
llvm-svn: 146262
2011-12-09 18:09:40 +00:00
0a7f336475
Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a
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symbol difference. This matches gas behavior and fixes PR11513.
We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.
llvm-svn: 146238
2011-12-09 03:03:58 +00:00
db731be7b8
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
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llvm-svn: 146194
2011-12-08 22:19:04 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
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llvm-svn: 146192
2011-12-08 22:06:06 +00:00
3a97d946d2
Tidy up a bit.
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llvm-svn: 146190
2011-12-08 22:04:40 +00:00
ab9c8bb45b
ARM VSUB implied destination operand form aliases.
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llvm-svn: 146182
2011-12-08 20:56:26 +00:00
27a33edfa0
Tidy up a bit.
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llvm-svn: 146181
2011-12-08 20:53:19 +00:00
66c9ad7642
ARM VQADD implied destination operand form aliases.
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llvm-svn: 146179
2011-12-08 20:49:43 +00:00
e9ee1092e1
ARM a few more VMUL implied destination operand form aliases.
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llvm-svn: 146177
2011-12-08 20:42:35 +00:00
00326406d4
ARM NEON two-operand aliases for VSHL(immediate).
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llvm-svn: 146125
2011-12-08 01:30:04 +00:00
f10a635eb4
ARM NEON two-operand aliases for VSHL(register).
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llvm-svn: 146123
2011-12-08 01:12:35 +00:00
6600f520b0
ARM optional destination operand variants for VEXT instructions.
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llvm-svn: 146114
2011-12-08 00:43:47 +00:00
5ff64c7141
Tidy up.
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llvm-svn: 146113
2011-12-08 00:41:54 +00:00
3050625a50
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
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llvm-svn: 146111
2011-12-08 00:31:07 +00:00
3b559ff3c5
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
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For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
90d961250b
ARM two-operand aliases for VAND/VEOR/VORR instructions.
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llvm-svn: 146095
2011-12-07 23:08:12 +00:00
3744a7febb
ARM two-operand aliases for VADDW instructions.
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llvm-svn: 146093
2011-12-07 23:01:10 +00:00
552691556c
ARM two-operand aliases for VADD instructions.
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llvm-svn: 146091
2011-12-07 22:52:54 +00:00
d6ae4ba002
Darwin assembler improved relocs when w/o subsections_via_symbols.
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When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
llvm-svn: 146054
2011-12-07 19:46:59 +00:00
18b0e5dca0
Thumb2 alias for long-form pop and friends.
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rdar://10542474
llvm-svn: 146046
2011-12-07 18:32:28 +00:00
7f882399b8
ARM support the .arm and .thumb directives for assembly mode switching.
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llvm-svn: 146042
2011-12-07 18:04:19 +00:00
721042fa3a
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
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llvm-svn: 146039
2011-12-07 17:51:15 +00:00
a4337ced68
Tidy up. Move MachO tests to MachO directory.
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llvm-svn: 146038
2011-12-07 17:50:28 +00:00
51416d5f00
test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.
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FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
llvm-svn: 145925
2011-12-06 06:48:26 +00:00
e303e24d77
ARM mode 'mul' operand ordering tweak.
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Same as r145922, just for ARM mode.
llvm-svn: 145923
2011-12-06 05:28:00 +00:00
5f143be8c5
Thumb2: MUL two-operand form encoding operand order fix.
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Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
llvm-svn: 145922
2011-12-06 05:03:45 +00:00
175c7d0da5
Thumb2 encoding choice correction for PLD.
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Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
5bdc0fbabd
test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.
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MC/MachO assumes x86.
llvm-svn: 145916
2011-12-06 03:56:05 +00:00
9105085b4a
Fix ARM handling of tBcc branch relaxation.
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rdar://10069056
llvm-svn: 145885
2011-12-06 01:08:19 +00:00
b8c719ccc6
Tweak ADDrr fix. Bad check for explicit .w
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llvm-svn: 145863
2011-12-05 22:27:04 +00:00
8b5e92577b
Update tests for r145860. Add a few new ones.
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llvm-svn: 145861
2011-12-05 22:21:28 +00:00
ec9ba98299
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
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rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
fdf9e1587a
ARM assembly parsing for the rest of the VMUL data type aliases.
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Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
7276397f41
ARM tests for VLD1 single lane w/ writeback.
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llvm-svn: 145713
2011-12-02 22:03:52 +00:00
e7dcbc8691
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
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Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
9430e284a9
Support for encoding all FMA4 instructions and tablegen patterns for all
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remaining FMA4 instructions and intrinsics with tests.
llvm-svn: 145525
2011-11-30 22:09:42 +00:00
7d8517b1d4
Add some tests for all-lanes VLD1 parsing.
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llvm-svn: 145512
2011-11-30 19:37:38 +00:00
5ee209ce3a
ARM assembly parsing and encoding for four-register VST1.
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llvm-svn: 145450
2011-11-29 22:58:48 +00:00
2a9c43649a
Enable some VST1 tests and add a few more.
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llvm-svn: 145443
2011-11-29 22:40:32 +00:00
de3a2118db
MC/X86/COFF: Allow quotes in names when targeting MS/Windows,
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as MC is the only assembler we support.
This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.
llvm-svn: 145409
2011-11-29 18:00:06 +00:00
6a144a2227
Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic.
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llvm-svn: 145171
2011-11-27 06:54:59 +00:00
97b3da5433
Add several new instructions supported by the latest MicroBlaze.
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These instructions are not generated by the backend yet, this will come in a later commit.
llvm-svn: 145161
2011-11-27 05:16:58 +00:00
0f9a1f5e6c
This patch contains support for encoding FMA4 instructions and
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tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
2011-11-25 19:33:42 +00:00
651db37352
X86: alias cqo to cqto.
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llvm-svn: 145121
2011-11-24 12:02:46 +00:00
f4d2e0d458
Remove obsolete test.
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The PLD encoding is checked via the .s file now.
llvm-svn: 144853
2011-11-16 22:50:38 +00:00
d3f02cbce9
Generalize the fixup info for ARM mode.
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We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
llvm-svn: 144852
2011-11-16 22:48:37 +00:00
d66cb5ab33
Update test for r144842.
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llvm-svn: 144851
2011-11-16 22:46:27 +00:00
Jim Grosbach