4e36a934dc
Splats can contain undef's; make sure to handle them correctly. PR11526.
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llvm-svn: 146299
2011-12-09 23:54:42 +00:00
6192b6570d
ARM assembly aliases for BIC<-->AND (immediate).
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When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
llvm-svn: 146283
2011-12-09 22:02:17 +00:00
1d54d2210a
Update test to something more sensible.
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llvm-svn: 146282
2011-12-09 21:54:10 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
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Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
dd998ff4df
[fast-isel] Add support for selecting insertvalue.
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rdar://10530851
llvm-svn: 146276
2011-12-09 20:09:54 +00:00
7e0a793183
Handle reloc_signed_4byte in here. Not doing so was a regression from my
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previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.
llvm-svn: 146273
2011-12-09 19:57:29 +00:00
e7739d484f
The second part of support for generating dwarf for assembly source files. This
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generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.
The next part will be to get the clang driver to enable this when assembling
a .s file. rdar://9275556
llvm-svn: 146262
2011-12-09 18:09:40 +00:00
16bbfbec66
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
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llvm-svn: 146257
2011-12-09 15:44:03 +00:00
d04d152998
Add -unroll-runtime for unrolling loops with run-time trip counts.
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Patch by Brendon Cahoon!
This extends the existing LoopUnroll and LoopUnrollPass. Brendon
measured no regressions in the llvm test suite with -unroll-runtime
enabled. This implementation works by using the existing loop
unrolling code to unroll the loop by a power-of-two (default 8). It
generates an if-then-else sequence of code prior to the loop to
execute the extra iterations before entering the unrolled loop.
llvm-svn: 146245
2011-12-09 06:19:40 +00:00
5895fa79d6
Forgot setting -march.
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llvm-svn: 146244
2011-12-09 06:15:00 +00:00
0a7f336475
Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a
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symbol difference. This matches gas behavior and fixes PR11513.
We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.
llvm-svn: 146238
2011-12-09 03:03:58 +00:00
8e16aac534
jalr should use t9 ($25) for indirect calls regardless of the relocation model
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specified.
llvm-svn: 146229
2011-12-09 01:45:12 +00:00
053a724483
Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.
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llvm-svn: 146219
2011-12-09 01:16:26 +00:00
fe970725cc
Fix infinite loop in DSE when deleting a free in a reachable loop that's also
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trivially infinite.
llvm-svn: 146197
2011-12-08 22:36:35 +00:00
b96bca81e7
Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
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llvm-svn: 146196
2011-12-08 22:30:45 +00:00
db731be7b8
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
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llvm-svn: 146194
2011-12-08 22:19:04 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
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llvm-svn: 146192
2011-12-08 22:06:06 +00:00
2a217be25f
Add various missing AVX patterns which was causing crashes. Sadly, the generated
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code looks pretty bad compared to SSE.
rdar://10538793
llvm-svn: 146191
2011-12-08 22:05:28 +00:00
3a97d946d2
Tidy up a bit.
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llvm-svn: 146190
2011-12-08 22:04:40 +00:00
ab9c8bb45b
ARM VSUB implied destination operand form aliases.
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llvm-svn: 146182
2011-12-08 20:56:26 +00:00
27a33edfa0
Tidy up a bit.
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llvm-svn: 146181
2011-12-08 20:53:19 +00:00
66c9ad7642
ARM VQADD implied destination operand form aliases.
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llvm-svn: 146179
2011-12-08 20:49:43 +00:00
e9ee1092e1
ARM a few more VMUL implied destination operand form aliases.
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llvm-svn: 146177
2011-12-08 20:42:35 +00:00
0b9b9da6c8
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
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llvm-svn: 146171
2011-12-08 19:32:14 +00:00
3294538546
Add test for r146163.
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llvm-svn: 146167
2011-12-08 19:21:39 +00:00
c09e4593b2
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
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sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
llvm-svn: 146157
2011-12-08 17:32:18 +00:00
0faa233439
test/CodeGen/X86/vec_compare-2.ll: Add explicit -mtriple=i686-linux.
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llvm-svn: 146152
2011-12-08 15:24:09 +00:00
26edb291ac
Fix a bug in the integer-promotion of bitcast operations on vector types.
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We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.
llvm-svn: 146150
2011-12-08 13:10:01 +00:00
a4bcf27dae
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
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llvm-svn: 146143
2011-12-08 07:55:03 +00:00
00326406d4
ARM NEON two-operand aliases for VSHL(immediate).
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llvm-svn: 146125
2011-12-08 01:30:04 +00:00
f10a635eb4
ARM NEON two-operand aliases for VSHL(register).
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llvm-svn: 146123
2011-12-08 01:12:35 +00:00
6600f520b0
ARM optional destination operand variants for VEXT instructions.
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llvm-svn: 146114
2011-12-08 00:43:47 +00:00
5ff64c7141
Tidy up.
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llvm-svn: 146113
2011-12-08 00:41:54 +00:00
3050625a50
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
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llvm-svn: 146111
2011-12-08 00:31:07 +00:00
3b559ff3c5
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
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For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
ae378af667
32 to 64-bit zext pattern.
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llvm-svn: 146096
2011-12-07 23:14:41 +00:00
90d961250b
ARM two-operand aliases for VAND/VEOR/VORR instructions.
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llvm-svn: 146095
2011-12-07 23:08:12 +00:00
3744a7febb
ARM two-operand aliases for VADDW instructions.
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llvm-svn: 146093
2011-12-07 23:01:10 +00:00
552691556c
ARM two-operand aliases for VADD instructions.
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llvm-svn: 146091
2011-12-07 22:52:54 +00:00
b2e05cb6b1
64-bit WrapperPICPat patterns.
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llvm-svn: 146086
2011-12-07 22:11:43 +00:00
c5b5a8d8b1
Modify LowerFCOPYSIGN to handle Mips64.
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llvm-svn: 146080
2011-12-07 21:48:50 +00:00
4a04a56a36
Fix 64-bit immediate patterns.
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llvm-svn: 146059
2011-12-07 20:10:24 +00:00
d6ae4ba002
Darwin assembler improved relocs when w/o subsections_via_symbols.
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When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
llvm-svn: 146054
2011-12-07 19:46:59 +00:00
18b0e5dca0
Thumb2 alias for long-form pop and friends.
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rdar://10542474
llvm-svn: 146046
2011-12-07 18:32:28 +00:00
7f882399b8
ARM support the .arm and .thumb directives for assembly mode switching.
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llvm-svn: 146042
2011-12-07 18:04:19 +00:00
721042fa3a
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
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llvm-svn: 146039
2011-12-07 17:51:15 +00:00
a4337ced68
Tidy up. Move MachO tests to MachO directory.
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llvm-svn: 146038
2011-12-07 17:50:28 +00:00
ed8b3e38ec
Support vector bitcasts in the AsmPrinter. PR11495.
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llvm-svn: 146001
2011-12-07 00:50:54 +00:00
0e58cba286
Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494.
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llvm-svn: 145996
2011-12-07 00:11:56 +00:00
0fc34bc2d3
delaying restore-cr changed assigned registers in some tests
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llvm-svn: 145963
2011-12-06 20:55:46 +00:00
Eli Friedman