Commit Graph

210 Commits

Author SHA1 Message Date
Jim Grosbach 44091c2f10 Refactor loop for better readability.
Excellent suggestion from Ben Kramer.

llvm-svn: 149417
2012-01-31 20:56:55 +00:00
Jim Grosbach b4d3a6af97 Add explanatory comment.
llvm-svn: 149416
2012-01-31 20:34:53 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code)
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Evan Cheng 6bb95253eb After r147827 and r147902, it's now possible for unallocatable registers to be
live across BBs before register allocation. This miscompiled 197.parser
when a cmp + b are optimized to a cbnz instruction even though the CPSR def
is live-in a successor.
        cbnz    r6, LBB89_12
...
LBB89_12:
        ble     LBB89_1

The fix consists of two parts. 1) Teach LiveVariables that some unallocatable
registers might be liveouts so don't mark their last use as kill if they are.
2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional
branch does not kill CPSR.

rdar://10676853

llvm-svn: 148168
2012-01-14 01:53:46 +00:00
Jakob Stoklund Olesen 20f1dd5faf Consider unknown alignment caused by OptimizeThumb2Instructions().
This function runs after all constant islands have been placed, and may
shrink some instructions to their 2-byte forms.  This can actually cause
some constant pool entries to move out of range because of growing
alignment padding.

Treat instructions that may be shrunk the same as inline asm - they
erode the known alignment bits.

Also reinstate an old assertion in verify(). It is correct now that
basic block offsets include alignments.

Add a single large test case that will hopefully exercise many parts of
the constant island pass.

<rdar://problem/10670199>

llvm-svn: 147885
2012-01-10 22:32:14 +00:00
Jakob Stoklund Olesen f09a316542 Accurately model hardware alignment rounding.
On Thumb, the displacement computation hardware uses the address of the
current instruction rouned down to a multiple of 4.  Include this
rounding in the UserOffset we compute for each instruction.

When inline asm is present, the instruction alignment may not be known.
Constrain the maximum displacement instead in that case.

This makes it possible for CreateNewWater() and OffsetIsInRange() to
agree about the valid displacements.  When they disagree, infinite
looping happens.

As always, test cases for this stuff are insane.

<rdar://problem/10660175>

llvm-svn: 147825
2012-01-10 01:34:59 +00:00
Jakob Stoklund Olesen 1a80e3a26b Catch runaway ARMConstantIslandPass even in -Asserts builds.
The pass is prone to looping, and it is better to crash than loop
forever, even in a -Asserts build.

<rdar://problem/10660175>

llvm-svn: 147806
2012-01-09 22:16:24 +00:00
Jakob Stoklund Olesen 690511137c Abort AdjustBBOffsetsAfter early when possible.
llvm-svn: 147685
2012-01-06 21:40:15 +00:00
Jakob Stoklund Olesen 9790187b6c Fix off-by-one error in bucket sort.
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.

<rdar://problem/10594653>

llvm-svn: 146767
2011-12-16 23:00:05 +00:00
Jakob Stoklund Olesen 5af144809e Don't adjust for alignment padding in OffsetIsInRange.
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.

When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.

llvm-svn: 146751
2011-12-16 19:10:00 +00:00
Jakob Stoklund Olesen 2a05f691ab Note ARM constant island alignment in the release notes.
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.

llvm-svn: 146739
2011-12-16 16:07:41 +00:00
Jakob Stoklund Olesen cba8e8c3e0 Enable proper constant island alignment by default.
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.

llvm-svn: 146690
2011-12-15 22:14:45 +00:00
Jakob Stoklund Olesen 9efd7ebf0a Consider CPE alignment in CreateNewWater().
An aligned constant pool entry may require extra alignment padding where
the new water is created.  Take that into account when computing offset.

Also consider the alignment of other constant pool entries when
splitting a basic block.  Alignment padding may make it necessary to
move the split point higher.

llvm-svn: 146609
2011-12-14 23:48:54 +00:00
Jakob Stoklund Olesen e5585e8fed Fix speling and 80-col.
llvm-svn: 146575
2011-12-14 18:49:13 +00:00
Jakob Stoklund Olesen bfa576fe8e Account for CPE alignment when searching for new water.
Constant pool entries with different alignment may cause more alignment
padding to be inserted. Compute the amount of padding needed, and try to
pick the location that requires the least amount of padding.

Also take the extra padding into account when the water is above the
use.

llvm-svn: 146458
2011-12-13 00:44:30 +00:00
Jakob Stoklund Olesen 91a7bcbb9b Add a postOffset() alignment argument.
This computes the offset of the layout sucessor block, considering its
alignment as well.

llvm-svn: 146401
2011-12-12 19:25:54 +00:00
Jakob Stoklund Olesen 0863de458d Fix typo.
llvm-svn: 146400
2011-12-12 19:25:51 +00:00
Jakob Stoklund Olesen 17c27a8898 Also set the proper alignment on inner islands and the function itself.
Downgrade the alignment of the initial constant island when constant
pool entries are moved elsewhere.

This is all gated by -arm-align-constant-islands.

llvm-svn: 146391
2011-12-12 18:45:45 +00:00
Jakob Stoklund Olesen 2a75997858 Make MF a class member instead of passing it around everywhere.
Also add an MCP member pointing to the machine constant pool.

No functional change intended.

llvm-svn: 146382
2011-12-12 18:16:53 +00:00
Jakob Stoklund Olesen b5f52aad22 Add a -arm-align-constant-islands flag, default off.
Order constant pool entries by descending alignment in the initial
island to ensure packing and correct alignment.  When the command line
flag is set, also align the basic block containing the constant pool
entries.

This is only a partial implementation of constant island alignment. More
to come.

llvm-svn: 146375
2011-12-12 16:49:37 +00:00
Jakob Stoklund Olesen 146ac7b609 Try to align the point where a large basic block is split.
The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.

This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.

<rdar://problem/10550705>

There is still an issue with correctly packing differently aligned
entries in the island.

llvm-svn: 146314
2011-12-10 02:55:10 +00:00
Jakob Stoklund Olesen b3734522fa More debug output formatting.
llvm-svn: 146313
2011-12-10 02:55:06 +00:00
Jakob Stoklund Olesen f85723626c User a helper overload for a common pattern.
llvm-svn: 146270
2011-12-09 19:44:39 +00:00
Jakob Stoklund Olesen 5f5fa12413 Tweak debugging output.
llvm-svn: 146264
2011-12-09 18:20:35 +00:00
Jakob Stoklund Olesen 14e024dff7 Drop the HasInlineAsm flag.
It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.

A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.

llvm-svn: 146124
2011-12-08 01:22:39 +00:00
Jakob Stoklund Olesen bd97f5d753 Simplify offset verification.
llvm-svn: 146121
2011-12-08 01:10:05 +00:00
Jakob Stoklund Olesen 2a82333f54 Don't include alignment padding in BBInfo.Size.
Compute alignment padding before and after basic blocks dynamically.

Heed basic block alignment.

This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size.  It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.

This makes the ARMConstantIslandPass aware of aligned basic blocks.

It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size.  If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected.  This could cause constant
pool entries to move out of range.

To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly.  Normal
functions should be unaffected.

llvm-svn: 146118
2011-12-08 00:55:02 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Jakob Stoklund Olesen 2f0400b780 Eliminate delta argument from AdjustBBOffsetsAfter.
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.

Eliminate one redundant AdjustBBOffsetsAfter call.

llvm-svn: 146018
2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen 97c857199e Compute some alignment information for each basic block.
These fields are not used for anything yet.

llvm-svn: 146017
2011-12-07 04:17:35 +00:00
Jakob Stoklund Olesen af748e1180 Move common expression into a method.
llvm-svn: 146008
2011-12-07 01:22:52 +00:00
Jakob Stoklund Olesen e2b3ff2a07 Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
No functional change is intended.

llvm-svn: 146005
2011-12-07 01:08:25 +00:00
Jakob Stoklund Olesen cc6bfa8e79 Revert r145971: "Use conservative size estimate for tBR_JTr."
This caused more offset errors.

llvm-svn: 145980
2011-12-06 22:41:31 +00:00
Jakob Stoklund Olesen 33fe130e12 Use conservative size estimate for tBR_JTr.
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.

It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.

llvm-svn: 145971
2011-12-06 21:55:39 +00:00
Jakob Stoklund Olesen 2fa7448f31 Remove alignment from deserted constant islands.
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.

This should fix the many Thumb1 assembler errors in the nightly test
suite.

The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.

<rdar://problem/10534709>

llvm-svn: 145970
2011-12-06 21:55:35 +00:00
Jakob Stoklund Olesen 2e05db2fa0 Align ARM constant pool islands via their basic block.
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

llvm-svn: 145890
2011-12-06 01:43:02 +00:00
Jakob Stoklund Olesen 2608157f79 Use an existing function.
llvm-svn: 145883
2011-12-06 00:51:12 +00:00
Owen Anderson 3543398bcf There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404>
llvm-svn: 139531
2011-09-12 20:07:22 +00:00
Owen Anderson 93cd31869b Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB.
llvm-svn: 139429
2011-09-09 23:05:14 +00:00
Owen Anderson 29cfe6c368 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
Evan Cheng a20cde31e7 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
Owen Anderson 64d53620aa Re-apply r135319 with a fix for the constant island pass.
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135414
2011-07-18 18:50:52 +00:00
Jim Grosbach 7471937ad7 Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.

llvm-svn: 134746
2011-07-08 21:50:04 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Evan Cheng 88530e6568 Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
llvm-svn: 128743
2011-04-01 22:09:28 +00:00
Duncan Sands 75b5d27b84 Spelling fix: consequtive -> consecutive.
llvm-svn: 125563
2011-02-15 09:23:02 +00:00
Owen Anderson 4ebf471c9b Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
llvm-svn: 125127
2011-02-08 22:39:40 +00:00
Evan Cheng 558ccef74f Temporary workaround for a bad bug introduced by r121082 which replaced
t2LDRpci with t2LDRi12.
There are a couple of problems with this.
1. The encoding for the literal and immediate constant are different.
   Note bit 7 of the literal case is 'U' so it can be negative.
2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run.
   So we end up never using the Thumb2 instruction, which ends up creating a
   lot more constant islands.

llvm-svn: 125074
2011-02-08 03:07:03 +00:00
Anton Korobeynikov 221f4faa92 Save a mapping between original and cloned constpool entries.
llvm-svn: 124570
2011-01-30 22:07:39 +00:00
Evan Cheng dfce83c8f5 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
2011-01-17 08:03:18 +00:00