Commit Graph

20765 Commits

Author SHA1 Message Date
Jim Grosbach 09b602d85c Thumb2 asm aliases for wide bitwise w/ immediate instructions.
llvm-svn: 151384
2012-02-24 19:06:05 +00:00
Michael J. Spencer 248d65e78b Add WIN_FTOL_* psudo-instructions to model the unique calling convention
used by the Win32 _ftol2 runtime function. Patch by Joe Groff!

llvm-svn: 151382
2012-02-24 19:01:22 +00:00
Hal Finkel a3e6ed2161 X11/X2 loads around indirect calls on ppc64 should not be deleted.
llvm-svn: 151374
2012-02-24 17:54:01 +00:00
Richard Osborne de47462012 Remove dead code.
Patch by Ahmed Charles

llvm-svn: 151360
2012-02-24 11:49:08 +00:00
Pete Cooper 682c76b7d4 Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics
llvm-svn: 151342
2012-02-24 03:51:49 +00:00
Jia Liu 683f8fffcf comment fix
llvm-svn: 151341
2012-02-24 02:17:26 +00:00
Jia Liu 74aa025d68 some comment fix
llvm-svn: 151340
2012-02-24 02:15:57 +00:00
Jia Liu 13830229fd comment fix
llvm-svn: 151339
2012-02-24 02:15:21 +00:00
Jia Liu 9d2d2adc25 replace a balnk with -
llvm-svn: 151337
2012-02-24 02:05:28 +00:00
Jia Liu 19b0c8244b 80 columns of Mips InstPrinter Makefile
llvm-svn: 151332
2012-02-24 01:47:01 +00:00
Jakob Stoklund Olesen fa7a53746c Switch ARM target to register masks.
I'll let the buildbots determine the compile time improvements from this
change, but 464.h264ref has 5% faster codegen at -O2.

This patch does cause some assembly changes.  Branch folding can make
different decisions about calls with dead return values.
CriticalAntiDepBreaker may choose different registers because its
liveness tracking is affected.  MachineCopyPropagation may sometimes
leave a dead copy behind.

llvm-svn: 151331
2012-02-24 01:19:29 +00:00
Jim Grosbach 3a21e2c33e Make sure the regs are low regs for tMUL size reduction.
llvm-svn: 151318
2012-02-24 00:53:11 +00:00
Jim Grosbach c01104dfbf Thumb2 size reduction fix for tied operands of tMUL.
The tied source operand of tMUL is the second source operand, not the
first like every other two-address thumb instruction. Special case it
in the size reduction pass to make sure we create the tMUL instruction
properly.

llvm-svn: 151315
2012-02-24 00:33:36 +00:00
Dan Gohman d4a77c4682 When emitting a cmp with 0 for a lowered select, mask out the high
bits of the value carying the boolean condition, as their contents
are undefined. This fixes rdar://10887484.

llvm-svn: 151310
2012-02-24 00:09:36 +00:00
Roman Divacky a2d3608f78 MCize function entry label emission on PowerPC64 properly.
llvm-svn: 151278
2012-02-23 20:28:39 +00:00
Kevin Enderby 6fbcd8d439 Updated the llvm-mc disassembler C API to support for the X86 target.
rdar://10873652

As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back.  If there is a
getOpInfo call back that is tried first and then if that gets no information
then the  SymbolLookUp is called.  I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo.  And also don't use any
values from the  LLVMOpInfo1 struct if getOpInfo returns 0.  And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683

For the X86 target also fixed bugs so the annotations get printed. 

Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions.  rdar://10878166

llvm-svn: 151267
2012-02-23 18:18:17 +00:00
Brendon Cahoon d5d166d4d4 Fix the numbering of some of the registers and reclassify a couple of them.
Also, some basic clean up.  Patch by Evandro Menezes.

llvm-svn: 151266
2012-02-23 18:17:17 +00:00
Duncan Sands a354d58f8d Remove unused variable.
llvm-svn: 151251
2012-02-23 11:01:22 +00:00
Evan Cheng f258a15bdf Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16 bits
of x are zero. This optimizes rev + lsr 16 to rev16.

rdar://10750814

llvm-svn: 151230
2012-02-23 02:58:19 +00:00
Evan Cheng e87681cf34 Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
    cmp   r9, r4
    mov   r4, #0
    moveq r4, #1 
    orr   lr, lr, r4

should be:
    cmp   r9, r4
    orreq lr, lr, #1

That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).

It's possible to extend this to ADD and SUB but I don't think they are common.

rdar://8659097

llvm-svn: 151224
2012-02-23 01:19:06 +00:00
Hal Finkel ad4d9f5848 Allow the use of an alternate symbol for calculating a function's size.
The standard function epilog includes a .size directive, but ppc64 uses
an alternate local symbol to tag the actual start of each function.

Until recently, binutils accepted the .size directive as:
 .size	test1, .Ltmp0-test1
however, using this directive with recent binutils will result in the error:
 .size expression for XXX does not evaluate to a constant
so we must use the label which actually tags the start of the function.

llvm-svn: 151200
2012-02-22 21:11:47 +00:00
Michael J. Spencer 8b98bf2d6b Properly emit _fltused with FastISel. Refactor to share code with SDAG.
Patch by Joe Groff!

llvm-svn: 151183
2012-02-22 19:06:13 +00:00
Chad Rosier 5dfe6dab25 Remove extra semi-colons.
llvm-svn: 151169
2012-02-22 17:25:00 +00:00
Sirish Pande 2a783d5b94 Efficient pattern for store truncate. Patch by Evandro Menezes.
llvm-svn: 151166
2012-02-22 16:45:10 +00:00
Craig Topper cc830f8cda Declare register classes as const. Fix a couple pointers to register classes that weren't already const.
llvm-svn: 151138
2012-02-22 07:28:11 +00:00
Craig Topper 760b134ffa Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
llvm-svn: 151134
2012-02-22 05:59:10 +00:00
Aaron Ballman e67173e718 Adding support for Microsoft's thiscall calling convention. LLVM side of the patch.
llvm-svn: 151123
2012-02-22 03:04:40 +00:00
Jakob Stoklund Olesen 5f37f1c39d Clarify ARM calling conventions.
llvm-svn: 151113
2012-02-22 01:07:19 +00:00
Akira Hatanaka a7721f6b4d Use a function in MathExtras to do sign extension.
llvm-svn: 151107
2012-02-22 00:16:54 +00:00
Jakob Stoklund Olesen 6909faaf35 Calls don't really change the stack pointer.
Even if a call instruction has %SP<imp-def> operands, it doesn't change
the value of the stack pointer.

llvm-svn: 151104
2012-02-21 23:47:43 +00:00
Evan Cheng 0460ae8d80 Proper support for a bastardized darwin-eabi hybird ABI.
llvm-svn: 151083
2012-02-21 20:46:00 +00:00
Andrew Trick da84e64683 Clear virtual registers after they are no longer referenced.
Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0.
This makes sharing code for pre/postRA passes more robust.
Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA().
To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs().

PEI resets virtual regs when it's done scavenging.

PTX will either have to provide its own PEI pass or assign physregs.

llvm-svn: 151032
2012-02-21 04:51:23 +00:00
James Molloy 547d4c0662 Improve generated code for extending loads and some trunc stores on ARM.
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32.

llvm-svn: 150956
2012-02-20 09:24:05 +00:00
Ahmed Charles 636a3d618c Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
llvm-svn: 150918
2012-02-19 11:37:01 +00:00
Craig Topper de121a1000 Remove some unneeded includes and fix ordering in X86ISelLowering.cpp. Remove unneeded 'using namespace'.
llvm-svn: 150916
2012-02-19 07:15:48 +00:00
Craig Topper 65a4ceea1e Unify all shuffle mask checking functions take a mask and VT instead of VectorShuffleSDNode.
llvm-svn: 150913
2012-02-19 05:41:45 +00:00
Craig Topper 3e5c04e432 Make a bunch of X86ISelLowering shuffle functions static now that they are no longer needed by isel.
llvm-svn: 150908
2012-02-19 02:53:47 +00:00
Jia Liu 608dc6e257 comment fix ARM.h
llvm-svn: 150904
2012-02-19 02:04:03 +00:00
Jia Liu e1d619691b some comment fix for X86 and ARM
llvm-svn: 150902
2012-02-19 02:03:36 +00:00
Craig Topper 66a3597a4a Add vmfunc instruction to X86 assembler and disassembler.
llvm-svn: 150899
2012-02-19 01:39:49 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Craig Topper 57d3aaed78 Add X86InstrSVM.td that I forgot to add in r150873.
llvm-svn: 150874
2012-02-18 08:34:12 +00:00
Craig Topper ed7aa46366 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
llvm-svn: 150873
2012-02-18 08:19:49 +00:00
Jakob Stoklund Olesen 4fad5b2b9e Handle regmask operands in ARMInstrInfo.
llvm-svn: 150833
2012-02-17 19:23:15 +00:00
Jakob Stoklund Olesen 96732a438d Fix ARMBaseInstrInfo::getInstrLatency for calls.
Calls always clobber CPSR.

llvm-svn: 150831
2012-02-17 19:07:59 +00:00
Jia Liu 9f6101191b remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.
llvm-svn: 150805
2012-02-17 08:55:11 +00:00
Craig Topper ba172d2d59 Remove the last of the old vector_shuffle patterns from X86 isel.
llvm-svn: 150795
2012-02-17 07:02:34 +00:00
Akira Hatanaka d608bac682 Do not promote i32 arguments to i64. This was causing unnecessary sign extension
instructions to be emitted.

llvm-svn: 150782
2012-02-17 02:20:26 +00:00
Jia Liu dd6c1cd4e8 add Emacs tag and fix some comment error in file headers
llvm-svn: 150775
2012-02-17 01:23:50 +00:00
Chad Rosier fcd29ae390 [fast-isel] Add support for returning non-legal types with no sign- or zero-
entend flag.

llvm-svn: 150774
2012-02-17 01:21:28 +00:00