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21380 Commits

Author SHA1 Message Date
Jeff Cohen c7cb351aac Keep VC++ happy. 
llvm-svn: 24835
 2005-12-18 22:20:05 +00:00
Chris Lattner 2f5fb6a720 This is handled by the autogen'd code 
llvm-svn: 24834
 2005-12-18 21:06:11 +00:00
Chris Lattner f7ae0a95fe Handle basic block nodes 
llvm-svn: 24833
 2005-12-18 21:05:44 +00:00
Chris Lattner 1958690ff2 Change return lowering so that we can autogen the matching code. 
llvm-svn: 24832
 2005-12-18 21:03:04 +00:00
Chris Lattner 1febcd672c Add an accessor 
llvm-svn: 24831
 2005-12-18 21:00:53 +00:00
Chris Lattner 02e9904ee5 Implement Calls for V8. This would be completely autogenerated except for 
a small bug in tblgen.  When that is fixed, we can remove the ISD::Call case
in Select.

llvm-svn: 24830
 2005-12-18 15:55:15 +00:00
Chris Lattner abb11cc83e More fixes for Selection of copyto/fromreg with a flag 
llvm-svn: 24829
 2005-12-18 15:45:51 +00:00
Chris Lattner ebcfa0c210 More corrections for flagged copyto/from reg 
llvm-svn: 24828
 2005-12-18 15:36:21 +00:00
Chris Lattner fc3d4f8fd8 Select copytoreg and copyfromreg nodes that have flag operands correctly. 
llvm-svn: 24827
 2005-12-18 15:28:25 +00:00
Chris Lattner e3c67e97c7 legalize copytoreg and copyfromreg nodes that have flag operands correctly. 
llvm-svn: 24826
 2005-12-18 15:27:43 +00:00
Chris Lattner a0be18c9a4 Implement the full V8 ABI for incoming arguments. 
llvm-svn: 24825
 2005-12-18 13:33:06 +00:00
Chris Lattner 8d1db078cb Push ops list, asm string, and pattern all the way up to InstV8. Move the 
InstV8 class to the InstrFormats file where it belongs.

llvm-svn: 24824
 2005-12-18 08:21:00 +00:00
Chris Lattner 7cee2c9a5b Give V8 select_cc, in the spirit of the PPC backend 
llvm-svn: 24823
 2005-12-18 08:13:54 +00:00
Chris Lattner 9de2958138 remove some unused instructions 
llvm-svn: 24822
 2005-12-18 07:15:17 +00:00
Chris Lattner a9f0d108b1 V8 doesn't have FP extload 
llvm-svn: 24821
 2005-12-18 07:13:32 +00:00
Chris Lattner d6806875d0 simplifications, fix typo 
llvm-svn: 24820
 2005-12-18 07:09:06 +00:00
Chris Lattner c5609aab11 add a node, for completeness 
llvm-svn: 24819
 2005-12-18 07:05:21 +00:00
Chris Lattner 4492b1b7a0 Add frameindex support 
Add support for copying (e.g. returning) doubles
Add support for F<->I instructions

llvm-svn: 24818
 2005-12-18 06:59:57 +00:00
Chris Lattner 9dcfe37e76 Tighten up some checks 
llvm-svn: 24817
 2005-12-18 06:40:34 +00:00
Jim Laskey c97b7d0be9 Fix a bug Sabre was having where the DAG root was a group. The group dominator 
needed to be added to the ordering list, not the first member of the group.

llvm-svn: 24816
 2005-12-18 04:40:52 +00:00
Jim Laskey e220821deb Groups were not emitted if the dominator node and the node in the ordering list 
were not the same node.  Ultimately the test was bogus.

llvm-svn: 24815
 2005-12-18 03:59:21 +00:00
Nate Begeman 53c1f75090 Since extload can also be used by FP, split STDIntExtLoad into two parts, 
one for use with extload, one for use with sextload and zextload, which
are integer only.

llvm-svn: 24814
 2005-12-18 02:48:48 +00:00
Chris Lattner 5580e69df6 Add constant pool support, including folding into addresses. 
Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1]

llvm-svn: 24813
 2005-12-18 02:37:35 +00:00
Chris Lattner 726075fdf8 Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes, 
allowing us to compile this:

to this:

%G1 = external global int
%G2 = external global int
void %test() {
        %X = load int* %G1
        store int %X, int* %G2
        ret void
}

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        ld [%l0+%lo(G1)], %l0
        sethi %hi(G2), %l1
        st %l0, [%l1+%lo(G2)]
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        or %g0, %lo(G1), %l1
        ld [%l1+%l0], %l0
        sethi %hi(G2), %l1
        or %g0, %lo(G2), %l2
        st %l0, [%l2+%l1]
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 24812
 2005-12-18 02:27:00 +00:00
Chris Lattner a983c3df1c Add initial support for global variables, and fix a bug in addr mode selection 
where we didn't select the operands.

llvm-svn: 24811
 2005-12-18 02:10:39 +00:00
Chris Lattner a49b652a62 Claiming that branch targets are registers is not very wholesome. Change them 
to be basic blocks.  Also, add uncond branches.

llvm-svn: 24810
 2005-12-18 01:46:58 +00:00
Chris Lattner b29957500e Add unordered comparisons 
llvm-svn: 24809
 2005-12-18 01:41:39 +00:00
Chris Lattner e58481be36 Add patterns to the rest of the int condbranches and some of the fp branches 
llvm-svn: 24808
 2005-12-18 01:38:19 +00:00
Chris Lattner 9cf4bb2867 Add initial conditional branch support. This doesn't actually work yet due 
to a bug in the scheduler.

llvm-svn: 24807
 2005-12-18 01:20:35 +00:00
Chris Lattner cf12118965 Simplify code 
llvm-svn: 24806
 2005-12-18 01:03:46 +00:00
Chris Lattner 00759eac78 Eliminate CMPri, which is a synonym for SUBCCri 
llvm-svn: 24805
 2005-12-17 23:52:08 +00:00
Chris Lattner bf0bd99e03 allow custom expansion of BR_CC 
llvm-svn: 24804
 2005-12-17 23:46:46 +00:00
Chris Lattner 5a6b03c1b8 add fneg,fabs,fsqrt instructions 
llvm-svn: 24803
 2005-12-17 23:20:27 +00:00
Chris Lattner 32f19262d5 Add patterns for fround/fextend and the funny fsmuld instruction 
llvm-svn: 24802
 2005-12-17 23:14:30 +00:00
Chris Lattner 06952dfced Add FP +,-,*,/ 
llvm-svn: 24801
 2005-12-17 23:10:46 +00:00
Chris Lattner 89078880f2 Give patterns to F3_3 instructions 
llvm-svn: 24800
 2005-12-17 23:05:35 +00:00
Chris Lattner 829572cdca Implement 64-bit add/sub, make sure to receive and return 64-bit args with 
the right halves in the right regs

llvm-svn: 24799
 2005-12-17 22:55:57 +00:00
Chris Lattner ebfa06a2de implement div and rem 
llvm-svn: 24798
 2005-12-17 22:39:19 +00:00
Chris Lattner 8eaf9f4cb3 implement MULHU/MULHS for 64-bit multiplies 
llvm-svn: 24797
 2005-12-17 22:30:00 +00:00
Chris Lattner 4abe9528f9 Add patterns for multiply, simplify Y register handling stuff, add RDY instruction 
llvm-svn: 24796
 2005-12-17 22:22:53 +00:00
Chris Lattner 2616a0b56f Make the addressing modes smarter 
llvm-svn: 24795
 2005-12-17 21:25:27 +00:00
Chris Lattner 19ff62dc67 remove some unused instructions 
llvm-svn: 24794
 2005-12-17 21:13:50 +00:00
Chris Lattner e39ab718c0 add andn/orn/xorn patterns. This allows us to compile this: 
long %test(ubyte, short, long %X, long %Y) {
  %A = xor long %X, -1
  %B = and long %Y, %A
  ret long %B
}

to this:

test:
        save -96, %sp, %sp
        andn %i4, %i2, %i0
        andn %i5, %i3, %i1
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        xor %i2, -1, %l0
        xor %i3, -1, %l1
        and %i4, %l0, %i0
        and %i5, %l1, %i1
        restore %g0, %g0, %g0
        retl
        nop

The simpleisel emits:  :(

test:
        save -96, %sp, %sp
        or %g0, -1, %l0
        or %g0, -1, %l0
        or %g0, -1, %l0
        or %g0, -1, %l1
        xor %i2, %l0, %l0
        xor %i3, %l1, %l1
        and %i4, %l0, %i0
        and %i5, %l1, %i1
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 24793
 2005-12-17 21:05:49 +00:00
Chris Lattner ea752cc50a Add support for 64-bit arguments 
llvm-svn: 24792
 2005-12-17 20:59:06 +00:00
Chris Lattner 6be83f9959 Sparc doesn't have sext_inreg 
llvm-svn: 24791
 2005-12-17 20:50:42 +00:00
Chris Lattner d10995cb26 add patterns for FP stores 
llvm-svn: 24790
 2005-12-17 20:47:16 +00:00
Chris Lattner 490a6edf52 Add [reg+reg] integer stores 
llvm-svn: 24789
 2005-12-17 20:44:36 +00:00
Chris Lattner b57bb13253 Add store patterns 
llvm-svn: 24788
 2005-12-17 20:42:55 +00:00
Chris Lattner 233e044738 add truncstore 
llvm-svn: 24787
 2005-12-17 20:42:29 +00:00
Chris Lattner 7e7c355154 add fp load patterns, switch rest of loads and stores to use addrmodes 
llvm-svn: 24786
 2005-12-17 20:32:47 +00:00