835139bfe4
Iterate deterministicaly over ClassInfo*'s
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Fixes an observed instance of nondeterministic TableGen output.
Review by Jakob.
llvm-svn: 164191
2012-09-19 01:47:03 +00:00
c8f5657f91
Iterate deterministically over register classes
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Fixes an observed instance of nondeterministic TableGen output.
Review by Jakob.
llvm-svn: 164190
2012-09-19 01:47:01 +00:00
a4e2c5fc86
Refactor Record* by-ID comparator to Record.h
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This is a generally useful utility; there's no reason to have it hidden
in CodeGenDAGPatterns.cpp.
Also, rename it to fit the other comparators in Record.h
Review by Jakob.
llvm-svn: 164189
2012-09-19 01:47:00 +00:00
ef878a832b
FileCheck: Fix off-by-one bug that made CHECK-NOT: ignore the next character after the colon.
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llvm-svn: 164165
2012-09-18 20:51:39 +00:00
7ecfa6d960
Make custom operand parsing mnemonic indices use the same mnemonic table as the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets.
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llvm-svn: 164109
2012-09-18 07:02:21 +00:00
e2cfeb30a1
Use variable type for index into mnemonic table. Shrinks size of index field on in tree targets. Saving static data space.
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llvm-svn: 164108
2012-09-18 06:10:45 +00:00
ba7b921fcb
Replaced ReInitMCSubtargetInfo with InitMCProcessor.
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Now where we used to call ReInitMCSubtargetInfo, we actually recompute
the same information as InitMCSubtargetInfo instead of only setting
the feature bits.
llvm-svn: 164105
2012-09-18 05:33:15 +00:00
ea28dbdf93
comment typo
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llvm-svn: 164097
2012-09-18 04:03:30 +00:00
a88f1bddc6
TableGen subtarget emitter. Use getSchedClassIdx.
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llvm-svn: 164096
2012-09-18 03:55:55 +00:00
c6c88151bb
TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.
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llvm-svn: 164095
2012-09-18 03:41:43 +00:00
1188e439b2
TableGen subtarget emitter. Remove unnecessary header dependence.
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llvm-svn: 164094
2012-09-18 03:32:57 +00:00
ab722bdd50
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
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llvm-svn: 164092
2012-09-18 03:18:56 +00:00
9150610db7
Mark asm matcher conversion table as const.
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llvm-svn: 164088
2012-09-18 01:41:49 +00:00
aae8fb801e
Fix typo in comment. No functional change.
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llvm-svn: 164086
2012-09-18 01:13:36 +00:00
8038ceb731
Backout the wrong subtarget emitter fix
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llvm-svn: 164078
2012-09-17 23:14:15 +00:00
3e5546add7
Fix release build after reverting
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llvm-svn: 164075
2012-09-17 23:05:04 +00:00
8e7f202e32
Revert r164061-r164067. Most of the new subtarget emitter.
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I have to work out the Target/CodeGen header dependencies
before putting this back.
llvm-svn: 164072
2012-09-17 23:00:42 +00:00
692b87c18f
InitMCProcessor
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llvm-svn: 164066
2012-09-17 22:19:12 +00:00
c00f4314ce
comment typo
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llvm-svn: 164064
2012-09-17 22:19:04 +00:00
36e07eb83e
TableGen subtarget emitter. Use getSchedClassIdx.
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llvm-svn: 164063
2012-09-17 22:19:01 +00:00
7a1faa2c8a
TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.
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llvm-svn: 164062
2012-09-17 22:18:58 +00:00
0923f8183b
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
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llvm-svn: 164061
2012-09-17 22:18:55 +00:00
a72fca6bec
TableGen subtarget emitter. Format and emit data tables for the new machine model.
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llvm-svn: 164060
2012-09-17 22:18:50 +00:00
9ef0882b72
TableGen subtarget emitter. Generate data tables for the new machine model.
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Map the CodeGenSchedule object model onto data tables. The structure
of the data tables is defined in MC, so for convenience we include
MCSchedule.h. The alternative is maintaining a redundant copy of the
table structure definitions. Mapping the object model onto data tables
is sufficiently complicated that it should not be interleaved with
emitting source code. This avoids major problem with the backend for
itinerary generation.
llvm-svn: 164059
2012-09-17 22:18:48 +00:00
23f3c65e4b
TableGen subtarget emitter. Emit processor resources for the new machine model.
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llvm-svn: 164058
2012-09-17 22:18:45 +00:00
8fa00f5069
TableGen subtarget parser: Add getProcResourcesIdx().
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llvm-svn: 164057
2012-09-17 22:18:43 +00:00
4c36349de9
TableGen: Add initializer.
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Keep GCC's warnings happy. It can't reason out that the state machine won't
ever hit the potentially uninitialized use in OPC_FilterValue.
llvm-svn: 164041
2012-09-17 18:00:53 +00:00
4a1270691e
Fix a few vars that can end up being used without initialization.
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The cases where no initialization happens should still be checked for logic flaws.
llvm-svn: 164032
2012-09-17 14:20:57 +00:00
ebeedd0ed6
Fix typo
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llvm-svn: 164012
2012-09-17 04:43:39 +00:00
a583df034a
Add 'virtual' keywoards to output file for overridden functions.
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llvm-svn: 164002
2012-09-16 18:25:36 +00:00
8dcaf4998c
Add 'virtual' keywoards to output file for overridden functions.
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llvm-svn: 163999
2012-09-16 16:35:22 +00:00
8d30240939
Fix Doxygen issues: wrap code examples in \code and use \p to refer to
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parameters.
llvm-svn: 163984
2012-09-15 20:22:05 +00:00
f8f0a23ce7
Revert r163878 as it breaks on targets with alternate register names. Such targets do not exist in the main tree so this was not noticed.
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llvm-svn: 163959
2012-09-15 01:22:42 +00:00
1e46d48814
TableGen subtarget parser. Handle new machine model.
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Collect processor resources from the subtarget defs.
llvm-svn: 163953
2012-09-15 00:20:02 +00:00
33401e8469
TableGen subtarget parser. Handle new machine model.
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Infer SchedClasses from variants defined by the target or subtarget.
llvm-svn: 163952
2012-09-15 00:19:59 +00:00
766864963b
TableGen subtarget parser. Handle new machine model.
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Collect SchedClasses and SchedRW types from the subtarget defs.
llvm-svn: 163951
2012-09-15 00:19:57 +00:00
06cec4ceac
Allow the second opcode info table to be 8, 16, or 32-bits as needed to represent additional fragments. This recovers some space on ATT X86 syntax and PowerPC which only need 40-bits instead of 48-bits. This also increases ARM to 64-bits to fully encode all of its operands.
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llvm-svn: 163880
2012-09-14 08:33:11 +00:00
805e39beab
Reduce size of register name index tables by using uint16_t for all in tree targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead.
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llvm-svn: 163878
2012-09-14 06:37:49 +00:00
4d9ae56a45
AsmWriterEmitter: OpInfo2 should be unsigned 16-bit.
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Fix an issue in r163814.
llvm-svn: 163837
2012-09-13 20:47:48 +00:00
68cf9fc45d
AsmWriterEmitter: increase the number of bits for OpcodeInfo from 32-bit to
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48-bit if necessary, in order to reduce the generated code size.
We have 900 cases not covered by OpcodeInfo in ATT AsmWriter and more in Intel
AsmWriter and ARM AsmWriter.
This patch reduced the clang Release build size by 50k, running on a Mac Pro.
llvm-svn: 163814
2012-09-13 17:43:46 +00:00
2bc1d483fe
Fix Doxygen issues:
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* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
people want -- it starts a new paragraph).
llvm-svn: 163790
2012-09-13 12:34:29 +00:00
963305b450
Add a new compression type to ModRM table that detects when the memory modRM byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren.
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llvm-svn: 163774
2012-09-13 05:45:42 +00:00
f6cb1ee75a
TableGen: Convert an assert() to a proper diagnostic.
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llvm-svn: 163726
2012-09-12 17:40:25 +00:00
881929c1b6
Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.
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llvm-svn: 163721
2012-09-12 16:59:47 +00:00
16ba4b2d83
Improve tblgen code cleanliness: create an unknown_class, from which the unknown def inherits. Make tblgen check for that class, rather than checking for the def itself.
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llvm-svn: 163664
2012-09-11 23:47:08 +00:00
ccd682c695
Compute a map from register names to registers, rather than scanning the list of registers every time we want to look up a register by name.
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llvm-svn: 163659
2012-09-11 23:32:17 +00:00
d346d4871a
Add TRI::getSubRegIndexLaneMask().
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Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.
The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.
Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.
llvm-svn: 163630
2012-09-11 16:34:08 +00:00
dd40fda52d
Clean the sub-reg index composition maps at emission.
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Preserve the Composites map in the CodeGenSubRegIndex class so it can be
used to determine which sub-register indices can actually be composed.
llvm-svn: 163629
2012-09-11 16:34:05 +00:00
21e2f1c6e5
Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.
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Apparently, NumSubRegIndices was completely unused before. Adjust it by
one to include the null subreg index, just like getNumRegs() includes
the null register.
llvm-svn: 163628
2012-09-11 16:34:02 +00:00
8702c5b7c0
Change unsigned to a uint16_t in static disassembler tables to reduce the table size.
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llvm-svn: 163594
2012-09-11 04:19:21 +00:00
Sean Silva