Commit Graph

421313 Commits

Author SHA1 Message Date
Jan Svoboda 713e716cda [clang] NFCI: Use FileEntryRef in FileManagerTest
This patch removes use of the deprecated `{File,Directory}Entry::getName()` from `FileManager` unit tests by using `{File,Directory}EntryRef` instead.

Reviewed By: bnbarham

Differential Revision: https://reviews.llvm.org/D123770
2022-04-15 15:16:17 +02:00
Jan Svoboda 99b4874a53 [clang] NFCI: Use DirectoryEntryRef in collectIncludePCH
This patch removes use of the deprecated `DirectoryEntry::getName()` from `collectIncludePCH` by using `{File,Directory}EntryRef` instead.

Reviewed By: bnbarham

Differential Revision: https://reviews.llvm.org/D123769
2022-04-15 15:16:17 +02:00
Jan Svoboda 9d98f58959 [clang][CodeGen] NFCI: Use FileEntryRef
This patch removes use of the deprecated `DirectoryEntry::getName()` from clangCodeGen by using `{File,Directory}EntryRef` instead.

Reviewed By: bnbarham

Differential Revision: https://reviews.llvm.org/D123768
2022-04-15 15:16:17 +02:00
Jan Svoboda f263dac446 [clang][parse] NFCI: Use FileEntryRef in Parser::ParseModuleImport()
This patch removes use of the deprecated `DirectoryEntry::getName()` from `Parser` by using `{File,Directory}EntryRef` instead.

Reviewed By: bnbarham

Differential Revision: https://reviews.llvm.org/D123767
2022-04-15 15:16:17 +02:00
Aaron Ballman 33d3fc4466 [C89/C2x] Diagnose calls to a function without a prototype but passes arguments
This catches places where a function without a prototype is
accidentally used, potentially passing an incorrect number of
arguments, and is a follow-up to the work done in
https://reviews.llvm.org/D122895 and described in the RFC
(https://discourse.llvm.org/t/rfc-enabling-wstrict-prototypes-by-default-in-c).
The diagnostic is grouped under the new -Wdeprecated-non-prototypes
warning group and is enabled by default.

The diagnostic is disabled if the function being called was implicitly
declared (the user already gets an on-by-default warning about the
creation of the implicit function declaration, so no need to warn them
twice on the same line). Additionally, the diagnostic is disabled if
the declaration of the function without a prototype was in a location
where the user explicitly disabled deprecation warnings for functions
without prototypes (this allows the provider of the API a way to
disable the diagnostic at call sites because the lack of prototype is
intentional).
2022-04-15 09:08:54 -04:00
Lei Zhang 4db65e279b [mlir][vector] Reorder elementwise(transpose)
Similar to the existing pattern for reodering cast(transpose),
this makes transpose following transpose and increases the chance
of embedding the transposition inside contraction op. Actually
cast ops are just special instances of elementwise ops.

Reviewed By: ThomasRaoux

Differential Revision: https://reviews.llvm.org/D123596
2022-04-15 09:05:35 -04:00
Momchil Velikov 24c84bd236 [AArch64] Async unwind - Fix MTE codegen emitting frame adjustments in a loop
When untagging the stack, the compiler may emit a sequence like:
```
        .LBB0_1:
          st2g sp, [sp], #32
          sub x8, x8, #32
          cbnz x8, .LBB0_1
          stg sp, [sp], #16
```
These stack adjustments cannot be described by CFI instructions.

This patch disables merging of SP update with untagging, i.e. makes the
compiler use an additional scratch register (there should be plenty
available at this point as we are in the epilogue) and generate:
```
            mov     x9, sp
            mov     x8, #256
            stg     x9, [x9], #16
    .LBB0_1:
            sub     x8, x8, #32
            st2g    x9, [x9], #32
            cbnz    x8, .LBB0_1
            add     sp, sp, #272
```
Merging is disabled only when we need to generate asynchronous unwind
tables.

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D114548
2022-04-15 14:00:23 +01:00
Roman Lebedev 5865a74755
Require asserts in newly added test 2022-04-15 15:56:37 +03:00
Roman Lebedev 8fbed6870b
[UpdateTestChecks] Prevent rapid onset insanity when forced to write LoopVectorize-driven costmodel tests
Subj, or on other words, we have a lot of tests that are driven by
the LoopVectorizer's debug output, but we don't have
any meaningful way to autogenerate checklines in them,
which means that an insurmountable amount of manual work
is required when modifying the appropriate cost models.

That is not sustainable, so this presents a solution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D121133
2022-04-15 15:37:29 +03:00
LLVM GN Syncbot 4dba3d4c53 [gn build] Port 1d83750f63 2022-04-15 11:44:38 +00:00
Nikolas Klauser 1d83750f63 [libc++] Implement ranges::copy{, _n, _if, _backward}
Reviewed By: Mordante, var-const, #libc

Spies: sstefan1, libcxx-commits, mgorny

Differential Revision: https://reviews.llvm.org/D122982
2022-04-15 13:44:11 +02:00
zhongyunde 49cb4fef02 [AArch64][SelectionDAG] Refactor to support more scalable vector extending stores
Similar to D122281, we should firstly exclude all scalable vector extending
stores and then selectively enable those which we directly support.

Also merge integer and float scalable vector into scalable_vector_valuetypes.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D123449
2022-04-15 19:11:40 +08:00
Nico Weber f097885b07 [gn build] (manually) port 6d45558c1a (MipsGenPostLegalizeGICombiner) 2022-04-15 07:05:15 -04:00
Clement Courbet 46a13a0ef8 [ExpandMemCmp] Properly expand `bcmp` to an equality pattern.
Before that change, constant-size `bcmp` would miss an opportunity to generate
a more efficient equality pattern and would generate a -1/0-1 pattern
instead.

Differential Revision: https://reviews.llvm.org/D123849
2022-04-15 11:26:24 +02:00
Clement Courbet 866bd4df47 [NFC] Add test in preparation for D123849. 2022-04-15 11:15:29 +02:00
Brad Smith afa7c5ddc6 [WebAssembly] Remove TODO comment for IAS, NFC
IAS has been enabled on WebAssembly since commit 0a55d3f557.
2022-04-15 04:31:23 -04:00
Daniil Kovalev 8e43cbab33 [UpdateTestChecks] Add NVPTX support in update_llc_test_checks.py
This patch makes possible generating NVPTX assembly check lines with
update_llc_test_checks.py utility.

Differential Revision: https://reviews.llvm.org/D122986
2022-04-15 11:01:53 +03:00
Mehdi Amini 4197475eb0 Apply clang-tidy fixes for readability-identifier-naming in TestTypes.cpp (NFC) 2022-04-15 08:01:04 +00:00
Mehdi Amini 7a80912dd8 Apply clang-tidy fixes for modernize-use-default-member-init in ControlFlowSinkUtils.cpp (NFC) 2022-04-15 08:01:04 +00:00
Brad Smith 5206c2c167 [Driver] Move Lanai IAS enabling to Generic_GCC::IsIntegratedAssemblerDefault, NFC
Reviewed By: MaskRay, jpienaar

Differential Revision: https://reviews.llvm.org/D123836
2022-04-15 03:55:59 -04:00
Vitaly Buka b61f173f24 [lit] Forward more sanitizer env in TestingConfig 2022-04-15 00:50:52 -07:00
Vitaly Buka 43e0cedc1e [NFC] Reformat a part of TestingConfig.py 2022-04-15 00:50:52 -07:00
Lian Wang 545d353b3c [RISCV][NFC] Refactor VL patterns for vnsrl and vnsra
Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D123274
2022-04-15 07:42:59 +00:00
Fangrui Song b483ce1228 [ELF][ARM] Fix unneeded thunk for branches to hidden undefined weak
Similar to D123750 for AArch64.
2022-04-14 23:58:13 -07:00
Nicolai Hähnle f097088b05 AMDGPU: Add more mad_64_32 test cases
Test the behavior when a MUL is used multiple times, as well as when it
is uniform.

Run the tests for gfx9 as well, which added S_MUL_HI_[IU]32.
2022-04-15 00:38:37 -05:00
Chia-hung Duan 5232c5c5d4 [mlir] Fix verification order of nested ops.
In order to increase parallism, certain ops with regions and have the
IsIsolatedFromAbove trait will have their verification delayed. That
means the region verifier may access the invalid ops and may lead to a
crash.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D122771
2022-04-15 04:41:10 +00:00
Nicolai Hähnle 90a17ef6cc AMDGPU: Add mixed sign/zero-extend multiply-add test
There's a missed opportunity here that a later patch will exploit.
2022-04-14 23:34:45 -05:00
Peter Klausler e6873bfbcd [flang][runtime] Don't skip input spaces when they are significant
When formatted input (not list-directed or NAMELIST) is in "BZ" mode,
either because a BZ control edit descriptor appeared in a FORMAT or
BLANK="ZERO" appeared in OPEN or READ, input editing must not skip
over blanks before or within the input field.

Differential Revision: https://reviews.llvm.org/D123725
2022-04-14 21:30:43 -07:00
Thomas Raoux fa2762a251 [mlir] Update bazel file after adding nvgpu to nvvm conversion 2022-04-15 04:29:32 +00:00
Michael Liao f9486f2139 [LoongArch] Fix shared build. NFC. 2022-04-15 00:21:28 -04:00
Fangrui Song 98c22f68e6 [PGO][test] Fix memop_size_opt.ll 2022-04-14 21:16:04 -07:00
Fangrui Song d324d6b5dc [PGO][test] Remove duplicate --pgo-instr-memop tests 2022-04-14 21:13:43 -07:00
wanglei 407b613d73 [LoongArch] Add support for selecting constant materializations.
Integer materializing can generate LU12I_W, ORI, LU32I_D, LU52I_D and
ADDI_W instructions.

According to the sign-extended behavior of these instructions
(except ORI), the generated instruction sequence can be improved.

For example, load -1 into general register:
The ADDI_W instruction performs the operation that the [31:0] bit data
in the general register `rj` plus the 12-bit immediate `simm12` sign
extension 32-bit data; the resultant [31:0] bit is sign extension, then
written into the general register `rd`.

Normal sequence:

```
lu12i.w $a0, -1
ori $a0, $a0, 2048
```

Improved with sign-extended instruction:

```
addi.w $a0, $zero,  -1
```

Reviewed By: SixWeining, MaskRay

Differential Revision: https://reviews.llvm.org/D123290
2022-04-15 12:04:35 +08:00
Thomas Raoux 59058c441a [mlir][vector] Add operations used for Vector distribution
Add vector op warp_execute_on_lane_0 that will be used to do incremental
vector distribution in order to target warp level vector programming for
architectures with GPU-like SIMT programming model.
The idea behing the op is discussed further on discourse:
https://discourse.llvm.org/t/vector-vector-distribution-large-vector-to-small-vector/1983/23

Differential Revision: https://reviews.llvm.org/D123703
2022-04-15 03:47:52 +00:00
Fangrui Song b5d884a38c [PGO][test] Change opt -foo tests to -passes= and remove duplicates 2022-04-14 20:35:35 -07:00
Jacques Pienaar 35bd41916b [mlir] Add assert to fail with more info (NFC)
This would have assert before during tensor type construction with
opaque error, assert and fail earlier now.
2022-04-14 19:54:12 -07:00
jacquesguan 1aa4f0bb6c [RISCV][VP] Add RVV codegen for vp.trunc.
Differential Revision: https://reviews.llvm.org/D123579
2022-04-15 02:29:53 +00:00
Michael Williamson f4cc757560 Add missing word in llc docs 2022-04-14 22:29:03 -04:00
Amir Ayupov 2a9386726b [BOLT][NFC] Use LLVM_REVISION instead of BOLT_VERSION_STRING
Remove duplicate version string identification

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D123549
2022-04-14 19:16:35 -07:00
jacquesguan 3d79c52f31 [mlir][LLVMIR] Add more vector predication intrinsic ops.
This revision adds vector predication select, merge and load/store intrinsic ops.

Differential Revision: https://reviews.llvm.org/D123477
2022-04-15 02:13:42 +00:00
Fangrui Song 0cefd53d6e [gcov][test] Change some legacy PM tests to new PM and remove others 2022-04-14 19:12:14 -07:00
Matt Arsenault a1303b23c9 clang/AMDGPU: Define macro for -munsafe-fp-atomics
The HIP headers want to use this to swap the implementation of the
function, rather than relying on backend expansion of the generic
atomic instruction.

Fixes: SWDEV-332998
2022-04-14 22:04:59 -04:00
Matt Arsenault 6d45558c1a Mips/GlobalISel: Add stub post-legalizer combiner
This enables no combines, just adds the boilerplate for the new pass.
2022-04-14 22:04:59 -04:00
Xiaodong Liu 2d9b7fdaa3 [utils] Use git to checkout code instead of svn in building docker image
Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D123795
2022-04-15 01:41:14 +00:00
Mehdi Amini ffdba713f5 Fix MLIR website generation 2022-04-15 01:28:30 +00:00
Matt Arsenault f163106f39 llvm-reduce: Handle cloning MachineFrameInfo and stack objects
This didn't work at all before, and would assert on any frame
index. Also copy the other fields, which I believe should cover
everything. There are a few that are untested since MIR serialization
is apparently still missing them (isStatepointSpillSlot,
ObjectSSPLayout, and ObjectSExt/ObjectZExt).
2022-04-14 21:25:06 -04:00
Peter Klausler 2503f28648 [flang] Accept TYPE(intrinsic type) in declarations only for non-extension type
To avoid clashing with names of user derived types, the redundant
syntax TYPE(intrinsic type spec) must be interpreted as a monomorphic
derived type when "intrinsic type spec" is a single word.  This
affects TYPE(BYTE) and TYPE(DOUBLECOMPLEX), but not TYPE(DOUBLE COMPLEX)
in free form source.

Differential Revision: https://reviews.llvm.org/D123724
2022-04-14 18:19:37 -07:00
Dhruva Chakrabarti 7086a1db80 [libomptarget] [amdgpu] Hostcall offset check should consider implicit args
Fixed hostcall offset check to compare against kernarg segment size
and implicit arguments. Improved the corresponding debug print.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D123827
2022-04-15 00:53:47 +00:00
Matt Arsenault e33b07f859 llvm-reduce: Inform MRI of used phys reg masks
I'm not sure how to directly observe this invisible cache for a test.
2022-04-14 20:52:05 -04:00
Matt Arsenault 3217ca0863 llvm-reduce: Copy register allocation hints to clone 2022-04-14 20:52:05 -04:00