1b09836bc3
Change getFrameMoves to return a const reference.
...
To add a frame now there is a dedicated addFrameMove which also takes
care of constructing the move itself.
llvm-svn: 181657
2013-05-11 02:38:11 +00:00
bf0bd1f4ab
Fix unused variable error.
...
Earlier, this variable was used in an assert and was causing failure on
darwin.
llvm-svn: 181630
2013-05-10 21:44:02 +00:00
438cec566b
Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.
...
No functionality change.
llvm-svn: 181628
2013-05-10 20:58:11 +00:00
300f0b966c
Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.
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llvm-svn: 181624
2013-05-10 20:27:34 +00:00
140a837acd
Remove unused argument.
...
llvm-svn: 181618
2013-05-10 18:16:59 +00:00
7501a81a50
Remove unused function.
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llvm-svn: 181606
2013-05-10 16:53:12 +00:00
00681dc1f0
Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions.
...
No functionality change.
llvm-svn: 181535
2013-05-09 19:16:07 +00:00
978e972ff9
Hexagon: Use relation map for getMatchingCondBranchOpcode() and
...
getInvertedPredicatedOpcode() functions instead of switch cases.
llvm-svn: 181530
2013-05-09 18:25:44 +00:00
5eb598001c
Hexagon: Fix Small Data support to handle -G 0 correctly.
...
llvm-svn: 181344
2013-05-07 19:53:00 +00:00
03c6ca905c
Reverting r181331.
...
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt.
llvm-svn: 181334
2013-05-07 17:12:35 +00:00
19f0b40dcf
Hexagon: Fix Small Data support to handle -G 0 correctly.
...
llvm-svn: 181331
2013-05-07 16:42:15 +00:00
a03eb9b5d5
Hexagon: Set accessSize and addrMode on all load/store instructions.
...
llvm-svn: 181324
2013-05-07 15:06:29 +00:00
18ee1193bf
Print IR from Hexagon MI passes with -print-before/after-all.
...
llvm-svn: 181255
2013-05-06 21:58:00 +00:00
59df52c585
Cleanup of the HexagonTargetMachine setup.
...
llvm-svn: 181250
2013-05-06 21:25:45 +00:00
84c471029b
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
...
llvm-svn: 181235
2013-05-06 18:49:23 +00:00
d50074712f
Make references to HexagonTargetMachine "const".
...
llvm-svn: 181233
2013-05-06 18:38:37 +00:00
cd410d04db
Use consistent function names.
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llvm-svn: 181090
2013-05-04 01:30:49 +00:00
1c76f155b1
Fix missing include in Hexagon code for Release+Asserts
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llvm-svn: 180983
2013-05-03 00:54:56 +00:00
a841af7556
reverting r180953
...
llvm-svn: 180964
2013-05-02 22:10:59 +00:00
7e7c730c4f
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
...
llvm-svn: 180953
2013-05-02 21:21:57 +00:00
7dda912cd7
Hexagon - Add peephole optimizations for zero extends.
...
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
sequence of a pair of i32->i64 extensions followed by a "bitwise or"
into COMBINE_rr.
* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
* test/CodeGen/Hexagon/union-1.ll: New test.
* test/CodeGen/Hexagon/combine_ir.ll: Fix test.
llvm-svn: 180946
2013-05-02 20:22:51 +00:00
1d29750b7d
Hexagon: Honor __builtin_expect by using branch probabilities.
...
* lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp):
Given a jump opcode return the right pred.new jump opcode with
a taken vs not-taken hint based on branch probabilities provided
by the target independent module.
* lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function.
* lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode):
Enhance existing function use branch probabilities like
HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps.
llvm-svn: 180923
2013-05-02 15:39:30 +00:00
5ed5181178
Hexagon: Use multiclass for Jump instructions.
...
llvm-svn: 180885
2013-05-01 21:37:34 +00:00
cd66c0a270
Hexagon: Clear isKill flag on the predicate register in
...
PredicateInstruction function.
llvm-svn: 180884
2013-05-01 21:27:30 +00:00
af2359b98c
Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.
...
llvm-svn: 180145
2013-04-23 21:17:40 +00:00
f00aab98a0
Hexagon: Define relations for GP-relative instructions.
...
No functionality change.
llvm-svn: 180144
2013-04-23 21:05:55 +00:00
89c84821ea
Hexagon: Remove assembler mapped instruction definitions.
...
llvm-svn: 180133
2013-04-23 19:15:55 +00:00
a696239bec
Hexagon: Remove duplicate instructions to handle global/immediate values
...
for absolute/absolute-set addressing modes.
llvm-svn: 180120
2013-04-23 17:11:46 +00:00
a2b533906a
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
...
llvm-svn: 179939
2013-04-20 12:32:17 +00:00
b53d8963ce
ArrayRefize getMachineNode(). No functionality change.
...
llvm-svn: 179901
2013-04-19 22:22:57 +00:00
ce1be1130f
Hexagon: Set isPredicatedNew flag on predicate new instructions.
...
llvm-svn: 179388
2013-04-12 18:01:06 +00:00
bea8327fcb
Hexagon: Set isPredicatedFlase flag for all the instructions with negated predication.
...
llvm-svn: 179387
2013-04-12 17:46:52 +00:00
a929ab58c0
Hexagon: Expand br_cc.
...
It fixes following tests for Hexagon:
CodeGen/Generic/2003-07-29-BadConstSbyte.ll
CodeGen/Generic/2005-10-21-longlonggtu.ll
CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
CodeGen/Generic/MachineBranchProb.ll
CodeGen/Generic/builtin-expect.ll
CodeGen/Generic/pr12507.ll
llvm-svn: 178794
2013-04-04 21:18:26 +00:00
fee96f832d
Remove unused typedef.
...
llvm-svn: 178462
2013-04-01 13:46:15 +00:00
e1aa194aab
There is no longer any need to silence this compiler warning as the warning has
...
been turned off globally.
llvm-svn: 178451
2013-03-31 17:44:09 +00:00
add82b3c75
Hexagon: Add emitFrameIndexDebugValue function to emit debug information.
...
llvm-svn: 178368
2013-03-29 21:09:53 +00:00
26226cea4b
Hexagon: Disable DwarfUsesInlineInfoSection flag.
...
llvm-svn: 178345
2013-03-29 15:46:12 +00:00
a46059b74d
Hexagon: Replace switch-case in isDotNewInst with TSFlags.
...
llvm-svn: 178281
2013-03-28 19:44:04 +00:00
27c06f3322
Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.
...
llvm-svn: 178279
2013-03-28 19:34:49 +00:00
93e740485f
Hexagon: Use multiclass for gp-relative instructions.
...
Remove noV4T gp-relative instructions.
llvm-svn: 178246
2013-03-28 16:25:57 +00:00
d3490dc06a
Switch to LLVM support function abs64 to keep VS2008 happy.
...
llvm-svn: 178141
2013-03-27 13:15:08 +00:00
653d8839c8
Hexagon: Disable optimizations at O0.
...
llvm-svn: 178132
2013-03-27 11:14:24 +00:00
15957b129f
Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.
...
llvm-svn: 178032
2013-03-26 15:43:57 +00:00
f299668aeb
Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/HexagonMCInst.h.
...
llvm-svn: 178030
2013-03-26 15:34:22 +00:00
fdc660bf2e
Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.
...
llvm-svn: 177747
2013-03-22 18:41:34 +00:00
ec613665c2
Hexagon: Removed asserts regarding alignment and offset.
...
We are warning the user about the alignment, so we should not assert.
llvm-svn: 177103
2013-03-14 19:08:03 +00:00
df17ddd56b
Cleanup #includes.
...
llvm-svn: 176787
2013-03-10 13:11:23 +00:00
b1588fc057
DAGCombiner: Use correct value type for checking legality of BR_CC v3
...
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.
v2:
- Expand more BR_CC value types for NVPTX
v3:
- Expand correct BR_CC value types for Hexagon, Mips, and XCore.
llvm-svn: 176694
2013-03-08 15:36:57 +00:00
7825e064b9
Hexagon: Add patterns for zero extended loads from i1->i64.
...
llvm-svn: 176689
2013-03-08 14:15:15 +00:00
c7dcc2fbc5
Hexagon: Handle i8, i16 and i1 Var Args.
...
llvm-svn: 176647
2013-03-07 20:28:34 +00:00
Rafael Espindola