a8ab1b75cb
[Hexagon] Add support for Hexagon V65
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llvm-svn: 320404
2017-12-11 18:57:54 +00:00
557729761c
[Hexagon] Switch to parameterized register classes for HVX
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This removes the duplicate HVX instruction set for the 128-byte mode.
Single instruction set now works for both modes (64- and 128-byte).
llvm-svn: 313362
2017-09-15 15:46:05 +00:00
9c084fc55d
[Hexagon] Add intrinsics for data cache operations
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This is the LLVM part, adding definitions for
void @llvm.hexagon.Y2.dccleana(i8*)
void @llvm.hexagon.Y2.dccleaninva(i8*)
void @llvm.hexagon.Y2.dcinva(i8*)
void @llvm.hexagon.Y2.dczeroa(i8*)
void @llvm.hexagon.Y4.l2fetch(i8*, i32)
void @llvm.hexagon.Y5.l2fetch(i8*, i64)
The clang part will follow.
llvm-svn: 308032
2017-07-14 15:58:48 +00:00
65971d97b0
[Hexagon] Add intrinsics for masked vector stores
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Patch by Harsha Jagasia.
llvm-svn: 295879
2017-02-22 21:23:09 +00:00
f914278f8b
[Hexagon] Round 4 of selection pattern simplifications
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Give simpler or more meaningful names to pat frags and xforms.
llvm-svn: 286078
2016-11-06 18:09:56 +00:00
846597d081
[Hexagon] Round 3 of selection pattern simplifications
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Remove unnecessary C++ functions for SDNode transforms. Move more
pat frags to files where they are used.
llvm-svn: 286077
2016-11-06 18:05:14 +00:00
654dc11b79
[Hexagon] Rename operand/predicate names for unshifted integers
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For example, rename s6Ext to s6_0Ext. The names for shifted integers
include the underscore and this will make the naming consistent. It
also exposed a few duplicates that were removed.
llvm-svn: 285728
2016-11-01 19:02:10 +00:00
e57662d5ec
[Hexagon] Handle operand type differences for A2_tfrpi
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The instruction A2_tfrpi has a 64-bit operand, while the corresponding
intrinsic takes a 32-bit value. The actual value has only 8 significant
bits, so the difference is only in the type used to represent it.
In order to map the intrinsic to the instruction, the operand needs to
be extended to the correct type.
llvm-svn: 268635
2016-05-05 15:29:47 +00:00
040bb35d9d
[Hexagon] Use common Pat classes for selecting code for intrinsics
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llvm-svn: 267178
2016-04-22 18:05:55 +00:00
7d5b4db7f9
[Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
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We can generate the actual instructions from the intrinsics without the
need for pseudo-instructions. Also, since the intrinsics have a side-
effect in a form of a store, attempt to optimize away loads from the
store location.
llvm-svn: 260690
2016-02-12 17:01:51 +00:00
4eb6d4d1f2
[Hexagon] Hexagon V60 HVX intrinsic defintions
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Author: Ron Lieberman <ronl@codeaurora.org>
llvm-svn: 254165
2015-11-26 16:54:33 +00:00
05da79d5ac
[Hexagon] Remove the remnants of isConstExtProfitable
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llvm-svn: 250845
2015-10-20 19:04:53 +00:00
79ec06525e
[Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing intrinsic parameters to appropriate width.
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llvm-svn: 239634
2015-06-12 19:57:32 +00:00
47ab1f2007
[Hexagon] Intrinsics for circular and bit-reversed loads and stores
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llvm-svn: 232645
2015-03-18 16:23:44 +00:00
6d5a4b5dcd
Eliminate constant-extender profitability checks from Hexagon isel
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llvm-svn: 231992
2015-03-12 00:19:59 +00:00
27d50073b3
[Hexagon] Renaming A2_subri, A2_andir, A2_orir. Fixing formatting.
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llvm-svn: 228326
2015-02-05 18:38:08 +00:00
f297dbed48
[Hexagon] Renaming A2_addi and formatting.
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llvm-svn: 228318
2015-02-05 17:49:13 +00:00
cd9cb023d7
[Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic patterns and updating tests.
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llvm-svn: 228026
2015-02-03 20:40:52 +00:00
cf7248bcaf
[Hexagon] Updating XTYPE/PRED intrinsics.
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llvm-svn: 228019
2015-02-03 19:43:59 +00:00
e5daf3abfe
[Hexagon] Updating XTYPE/PERM intrinsics.
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llvm-svn: 228015
2015-02-03 19:36:59 +00:00
99cc7c1070
[Hexagon] Adding missing vector multiply instruction encodings. Converting multiply intrinsics and updating tests.
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llvm-svn: 228010
2015-02-03 19:15:11 +00:00
a6632452be
[Hexagon] Converting complex number intrinsics and adding tests.
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llvm-svn: 227995
2015-02-03 18:16:28 +00:00
cdba4e1bcc
[Hexagon] Adding vector intrinsics for alu32/alu and xtype/alu.
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llvm-svn: 227993
2015-02-03 18:01:45 +00:00
1610730faf
[Hexagon] Deleting old variants of intrinsics and adding missing tests.
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llvm-svn: 227474
2015-01-29 17:26:56 +00:00
e75aa4983c
[Hexagon] Deleting unused classes.
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llvm-svn: 227460
2015-01-29 16:35:38 +00:00
a749b3ee6a
[Hexagon] Adding XTYPE/PRED intrinsic tests. Converting predicate types to i32 instead of i1.
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llvm-svn: 227457
2015-01-29 16:08:43 +00:00
4379d10273
[Hexagon] Updating several V5 intrinsics and adding FP tests.
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llvm-svn: 227379
2015-01-28 22:08:16 +00:00
1de7e0d923
[Hexagon] Updating many V4 intrinsic patterns. Adding missing instruction and deleting unused classes.
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llvm-svn: 227353
2015-01-28 19:39:09 +00:00
94c33218e3
[Hexagon] Adding XTYPE/MPY intrinsic tests and some missing multiply instructions.
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llvm-svn: 227347
2015-01-28 19:16:17 +00:00
19ed07c75a
[Hexagon] Deleting a lot of old variants of intrinsics and updating references.
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llvm-svn: 227338
2015-01-28 18:29:11 +00:00
39b846ce0f
[Hexagon] Converting XTYPE/BIT intrinsic patterns and adding tests.
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llvm-svn: 227335
2015-01-28 18:06:23 +00:00
fe03c9a678
[Hexagon] Replacing XTYPE/SHIFT intrinsic patternss. Adding tests and missing instructions with tests.
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llvm-svn: 227330
2015-01-28 17:37:59 +00:00
fdbc5adbb6
[Hexagon] Replacing intrinsics for halfword adds and max/min word/dword.
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llvm-svn: 227322
2015-01-28 17:06:40 +00:00
94269db8ba
[Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns.
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llvm-svn: 226681
2015-01-21 18:13:15 +00:00
988c68f2a7
[Hexagon] Adding intrinsics for doubleword ALU operations.
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llvm-svn: 226606
2015-01-20 20:45:05 +00:00
0ee02fc9fe
[Hexagon] Updating muxir/ri/ii intrinsics. Setting predicate registers as compatible with i32 rather than doing custom type conversion.
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llvm-svn: 226500
2015-01-19 20:31:18 +00:00
fcd4569af6
[Hexagon] Converting intrinsics combine imm/imm, simple shifts and extends.
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llvm-svn: 226483
2015-01-19 18:56:19 +00:00
9327bdad2f
[Hexagon] Converting remaining ALU32/ALU intrinsics.
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llvm-svn: 226480
2015-01-19 18:33:58 +00:00
663419b008
[Hexagon] Converting ALU32/ALU intrinsics to new patterns.
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llvm-svn: 226478
2015-01-19 18:22:19 +00:00
310bad8b7e
[Hexagon] Converting halfword to double accumulating multiply intrinsics.
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llvm-svn: 226472
2015-01-19 17:36:32 +00:00
823415b881
[Hexagon] Converting halfword to doubleword multiply intrinsics.
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llvm-svn: 226326
2015-01-16 21:41:57 +00:00
cd9b276966
[Hexagon] Converting accumulating halfword multiply intrinsics to patterns.
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llvm-svn: 226324
2015-01-16 21:36:34 +00:00
3b047e0ee5
[Hexagon] Beginning converting intrinsics to patterns instead of duplicated definitions. Converting halfword multiply intrinsics.
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llvm-svn: 226318
2015-01-16 20:38:54 +00:00
402f772b82
[Hexagon] Adding doubleregs for control registers. Renaming control register class.
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llvm-svn: 224598
2014-12-19 18:56:10 +00:00
c50d64b07b
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.
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llvm-svn: 222801
2014-11-26 00:46:26 +00:00
31f7125562
Add missing attributes !cmp.[eq,gt,gtu] instructions.
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These instructions do not indicate they are extendable or the
number of bits in the extendable operand. Rename to match
architected names. Add a testcase for the intrinsics.
llvm-svn: 218453
2014-09-25 13:09:54 +00:00
9a103563f4
reverting r209132
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llvm-svn: 209139
2014-05-19 16:22:11 +00:00
daeb25d4e0
Hexagon: Add encoding bits to the mpy instructions.
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llvm-svn: 209132
2014-05-19 15:32:07 +00:00
83ccb6ce08
Hexagon V5 intrinsics support.
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llvm-svn: 156631
2012-05-11 19:39:13 +00:00
3c3bb55a85
Revert r155365, r155366, and r155367. All three of these have regression
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test suite failures. The failures occur at each stage, and only get
worse, so I'm reverting all of them.
Please resubmit these patches, one at a time, after verifying that the
regression test suite passes. Never submit a patch without running the
regression test suite.
llvm-svn: 155372
2012-04-23 18:25:57 +00:00
Krzysztof Parzyszek