b1457304cc
[mips] Define reg+imm load/store pattern templates.
...
llvm-svn: 178407
2013-03-30 02:01:48 +00:00
69fb3d11ec
[mips] Split SelectAddr, which was used to match address patterns, into two
...
functions. Set AddedComplexity to determine the order in which patterns are
matched.
This simplifies selection of floating point loads/stores.
No functionality change intended.
llvm-svn: 175300
2013-02-15 21:20:45 +00:00
28aed9ca85
[mips] Set flag neverHasSideEffects flag on some of the floating point instructions.
...
llvm-svn: 173401
2013-01-25 00:20:39 +00:00
873c724b4a
This patch tackles the problem of parsing Mips
...
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
llvm-svn: 172284
2013-01-12 01:03:14 +00:00
b1527b7505
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
...
parameter.
llvm-svn: 170661
2012-12-20 04:20:09 +00:00
b2cc8a756f
[mips] Delete all floating point instruction classes that are no longer used.
...
No functionality change.
llvm-svn: 170084
2012-12-13 02:05:02 +00:00
79e1cdb00b
[mips] Modify definitions of floating point comparison instructions.
...
No functionality change.
llvm-svn: 170077
2012-12-13 01:34:09 +00:00
fd9163b74c
[mips] Modify definitions of floating point branch instructions.
...
No functionality change.
llvm-svn: 170076
2012-12-13 01:32:36 +00:00
cd3dfd238e
[mips] Modify definitions of floating point indexed load and store instructions.
...
No functionality change.
llvm-svn: 170075
2012-12-13 01:30:49 +00:00
b0d4acbc65
[mips] Modify definitions of floating point multiply-add/sub instructions.
...
No functionality change.
llvm-svn: 170073
2012-12-13 01:27:48 +00:00
92994f4846
[mips] Modify definitions of floating point load and store instructions.
...
No functionality change.
llvm-svn: 170072
2012-12-13 01:24:00 +00:00
2b75dde5fa
[mips] Modify definitions of move from/to coprocessor instructions.
...
No functionality change.
llvm-svn: 170071
2012-12-13 01:16:49 +00:00
dea8f61ae0
[mips] Modify definitions of two register operand floating point instructions.
...
No functionality change.
llvm-svn: 170069
2012-12-13 01:14:07 +00:00
29b513871a
[mips] Modify definitions of three register operand floating point instructions
...
and separate encoding information from the rest.
llvm-svn: 170066
2012-12-13 01:07:37 +00:00
84693d5606
[mips] Move classes that do not belong in MipsInstrFormats.td into
...
MipsInstrFPU.td.
llvm-svn: 170061
2012-12-13 00:49:23 +00:00
db49b39200
[mips] Set isCommutable flag in a more explicit way.
...
llvm-svn: 170060
2012-12-13 00:46:23 +00:00
193e1f738a
[mips] Remove fmt from the parameter list of classes FMADDSUB and FNMADDSUB.
...
llvm-svn: 170057
2012-12-13 00:38:59 +00:00
caaf4dd516
[mips] Remove single-precision floating point instruction from multiclass
...
FFR2P_M.
llvm-svn: 170055
2012-12-13 00:35:54 +00:00
e986a59ad9
[mips] Remove single-precision floating point instructions from multiclasses
...
FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
llvm-svn: 170053
2012-12-13 00:29:29 +00:00
97e179f9e4
[mips] Shorten predicate name.
...
llvm-svn: 169579
2012-12-07 03:06:09 +00:00
3bc1beb696
[mips] Add predicate HasFPIdx for floating-point indexed load instruction
...
support and use it in place of HasMips32r2Or64.
llvm-svn: 168089
2012-11-15 21:17:13 +00:00
da1980f697
[mips] Set flag neverHasSideEffects flag on floating point conversion
...
instructions.
llvm-svn: 167348
2012-11-03 00:53:12 +00:00
3e7ba76157
Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and
...
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.
No changes in functionality.
llvm-svn: 163960
2012-09-15 01:52:08 +00:00
7605630c48
Add stub methods for mips assembly matcher.
...
Patch by Vladimir Medic.
llvm-svn: 162124
2012-08-17 20:16:42 +00:00
a66d676b20
Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether
...
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.
llvm-svn: 161071
2012-07-31 19:13:07 +00:00
4ce7c4060d
Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
...
single-precision load and store.
Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.
llvm-svn: 161063
2012-07-31 18:16:49 +00:00
d8ab16b86f
1. introduce MipsPat in place of Pat in order to exclude those from
...
being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered
Patch by Reed Kotler.
llvm-svn: 158470
2012-06-14 21:03:23 +00:00
cdf4fd8267
This patch adds a predicate to existing mips32 and mips64 so that those
...
instruction encodings can be excluded during mips16 processing.
This revision fixes the issue raised by Jim Grosbach.
bool hasStandardEncoding() const { return !inMips16Mode(); }
When micromips is added it will be
bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); }
No additional testing is needed other than to assure that there is no regression
from this patch.
Patch by Reed Kotler.
llvm-svn: 157234
2012-05-22 03:10:09 +00:00
71928e681b
Add disassembler to MIPS.
...
Patch by Vladimir Medic.
llvm-svn: 154935
2012-04-17 18:03:21 +00:00
47ad674f67
Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,
...
otherwise expand FNEG during legalization.
llvm-svn: 154546
2012-04-11 22:59:08 +00:00
7f4c9d1429
Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.
...
Invalid operation is signaled if the operand of these instructions is NaN.
llvm-svn: 154545
2012-04-11 22:49:04 +00:00
55059262aa
Revert r153924. There were buildbot failures.
...
llvm-svn: 153925
2012-04-03 02:51:09 +00:00
e2498d014b
MIPS disassembler support.
...
Patch by Vladimir Medic.
llvm-svn: 153924
2012-04-03 02:20:58 +00:00
6bbe1f0d10
Fix bugs which were introduced when support for base+index floating point loads
...
and stores was added.
- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.
llvm-svn: 151843
2012-03-01 22:12:30 +00:00
f54f60f3ce
remove blanks, and some code format
...
llvm-svn: 151625
2012-02-28 07:46:26 +00:00
330d901ce3
Add support for floating point base register + offset register addressing mode
...
load and store instructions.
llvm-svn: 151611
2012-02-28 02:55:02 +00:00
b260f206d2
Remove unnecessary template parameters.
...
llvm-svn: 151540
2012-02-27 19:17:53 +00:00
3c5cab4730
Fix instruction predicates that were not set correctly.
...
llvm-svn: 151538
2012-02-27 19:09:08 +00:00
60f7a8e710
Add definitions of floating point multiply add/sub and negative multiply
...
add/sub instructions.
llvm-svn: 151415
2012-02-25 00:21:52 +00:00
4705b0cc1c
Remove trailing whitespace. Add newline.
...
llvm-svn: 150706
2012-02-16 17:48:20 +00:00
77dbd786c8
Pattern for f32 to i64 conversion.
...
llvm-svn: 148869
2012-01-24 22:05:25 +00:00
2216f73676
Various Mips64 floating point instruction patterns.
...
llvm-svn: 144019
2011-11-07 21:38:58 +00:00
b2d37760a2
Add definition of the base class for floating point comparison instructions
...
and add Mips64's version too.
llvm-svn: 144018
2011-11-07 21:37:33 +00:00
1537e297e1
Add definitions of 64-bit instructions which move data between integer and
...
floating pointer registers.
llvm-svn: 144016
2011-11-07 21:32:58 +00:00
2312a3aaa0
Final patch that completes old JIT support for Mips:
...
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
llvm-svn: 142378
2011-10-18 17:50:36 +00:00
975bfc9b45
Move class and instruction definitions for conditional moves to a seperate file.
...
llvm-svn: 142220
2011-10-17 18:43:19 +00:00
b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
...
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
6be7d6c976
Simplify definition of FP move instructions.
...
llvm-svn: 141476
2011-10-08 03:50:18 +00:00
2365f90676
Define classes and multiclasses for FP binary instructions.
...
llvm-svn: 141475
2011-10-08 03:38:41 +00:00
c7548dec7d
Define multiclasses for FP-to-FP instructions.
...
llvm-svn: 141474
2011-10-08 03:29:22 +00:00
Akira Hatanaka