5 Commits

Author	SHA1	Message	Date
Craig Topper	9012028738	[X86] Don't use GR64 register 'and with immediate' instructions if the immediate is zero in the upper 33-bits or upper 57-bits. Use GR32 instructions instead. ... Previously the patterns didn't have high enough priority and we would only use the GR32 form if the only the upper 32 or 56 bits were zero. Fixes PR23100. llvm-svn: 234075	2015-04-04 02:08:20 +00:00
Jakob Stoklund Olesen	589c6eb95c	Remove -join-physregs from the test suite. ... This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027	2012-05-17 23:44:19 +00:00
Jakob Stoklund Olesen	17d4f9bbcc	Prepare remaining tests for -join-physreg going away. ... llvm-svn: 130893	2011-05-04 23:54:59 +00:00
Rafael Espindola	2216af3fa8	Fix another case where we were preferring instructions with large ... immediates instead of 8 bits ones. llvm-svn: 116410	2010-10-13 17:14:25 +00:00
Rafael Espindola	8ea9b0eb32	Fix PR8365 by adding a more specialized Pat that checks if an 'and' with ... 8 bit constants can be used. llvm-svn: 116403	2010-10-13 13:31:20 +00:00