Evan Cheng
8cd224e81c
Relex assertions to account for additional implicit def / use operands.
...
llvm-svn: 36430
2007-04-25 07:12:14 +00:00
Bill Wendling
9bfb1e1f29
What should be the last unnecessary <iostream>s in the library.
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llvm-svn: 32333
2006-12-07 22:21:48 +00:00
Evan Cheng
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
Chris Lattner
be9377a1e3
convert PPC::BCC to use the 'pred' operand instead of separate predicate
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value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
llvm-svn: 31835
2006-11-17 22:37:34 +00:00
Chris Lattner
e0263794f4
rename PPC::COND_BRANCH to PPC::BCC
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llvm-svn: 31834
2006-11-17 22:14:47 +00:00
Chris Lattner
8c6a41ea12
start using PPC predicates more consistently.
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llvm-svn: 31833
2006-11-17 22:10:59 +00:00
Evan Cheng
dc2c8748a7
Properly transfer kill / dead info.
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llvm-svn: 31765
2006-11-15 20:58:11 +00:00
Evan Cheng
dbd3d294e6
Matches MachineInstr changes.
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llvm-svn: 31712
2006-11-13 23:36:35 +00:00
Chris Lattner
113f7470e6
implement the BlockHasNoFallThrough hook
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llvm-svn: 31264
2006-10-28 17:35:02 +00:00
Chris Lattner
23f22de26f
Implement support for branch reversal, fix a bug in branch analysis.
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This provides stuff like:
cmpw cr0, r15, r29
mr r14, r15
- bge cr0, LBB3_111 ;bb656
- b LBB3_90 ;bb501
+ blt cr0, LBB3_90 ;bb501
LBB3_111: ;bb656
lwz r18, 68(r1)
which is particularly good for dispatch group formation.
llvm-svn: 31101
2006-10-21 06:03:11 +00:00
Chris Lattner
d881660366
Simplify code, no functionality change
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llvm-svn: 31097
2006-10-21 05:42:09 +00:00
Chris Lattner
94e04442eb
implement support for inserting a cond branch
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llvm-svn: 31096
2006-10-21 05:36:13 +00:00
Chris Lattner
a61f0105bd
add support for inserting an uncond branch
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llvm-svn: 31003
2006-10-17 18:06:55 +00:00
Chris Lattner
a47294ed7a
implement branch inspection/modification methods.
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llvm-svn: 30946
2006-10-13 21:21:17 +00:00
Chris Lattner
71227c23b1
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
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llvm-svn: 29096
2006-07-11 00:48:23 +00:00
Chris Lattner
52a956da52
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
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llvm-svn: 28889
2006-06-20 23:18:58 +00:00
Chris Lattner
49cadab385
Implement the getPointerRegClass method, which is required for the ptr_rc
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magic to work.
llvm-svn: 28847
2006-06-17 00:01:04 +00:00
Chris Lattner
10d6341618
Move some methods out of MachineInstr into MachineOperand
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llvm-svn: 28102
2006-05-04 17:52:23 +00:00
Chris Lattner
91400bd413
teach the ppc backend how to spill/reload vector regs
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llvm-svn: 26806
2006-03-16 22:24:02 +00:00
Chris Lattner
fd9f3e8ed3
Add support for copying registers. still needed: spilling and reloading them
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llvm-svn: 26800
2006-03-16 20:03:58 +00:00
Chris Lattner
ea79d9fd73
implement TII::insertNoop
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llvm-svn: 26562
2006-03-05 23:49:55 +00:00
Nate Begeman
4efb328926
add 64b gpr store to the possible list of isStoreToStackSlot opcodes.
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llvm-svn: 25916
2006-02-02 21:07:50 +00:00
Chris Lattner
c327d71e06
implement isStoreToStackSlot for PPC
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llvm-svn: 25914
2006-02-02 20:16:12 +00:00
Chris Lattner
bb53acd03c
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
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llvm-svn: 25913
2006-02-02 20:12:32 +00:00
Chris Lattner
5f37623218
teach ppc backend these are copies
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llvm-svn: 23813
2005-10-19 01:50:36 +00:00
Nate Begeman
0b71e007ef
First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
...
purely mechanical.
llvm-svn: 23778
2005-10-18 00:28:58 +00:00
Nate Begeman
6cca84e43c
More PPC32 -> PPC changes, as well as merging some classes that were
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redundant after the change.
llvm-svn: 23759
2005-10-16 05:39:50 +00:00
Chris Lattner
6f3b954662
Rename PPC32*.h to PPC*.h
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This completes the grand PPC file renaming
llvm-svn: 23745
2005-10-14 23:59:06 +00:00