else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
llvm-svn: 115466
1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.
llvm-svn: 115457
scheduling change in svn 115121. The CriticalAntiDepBreaker had bad
liveness information. It was calculating the KillIndices for one scheduling
region in a basic block, rescheduling that region so the KillIndices were
no longer valid, and then using those wrong KillIndices to make decisions
for the next scheduling region. I've not been able to reduce a small
testcase for this. Radar 8502534.
llvm-svn: 115400
where both symbols are "local", that is non-external symbols, and there is
no "base" for the symbols used in the expression, that is the section has
no non-temporary symbols. This case looks like this:
% cat local_reloc_A-B.s
.long 0
LB: .long 1
.long LA - LB - 4
.long 2
LA: .long 3
which llvm-mc will not encode without this patch, generates a "unsupported
local relocations in difference" error, but the Darwin assembler will
encode with relocation entries like this:
% otool -rv a.out l.out
a.out:
Relocation information (__TEXT,__text) 2 entries
address pcrel length extern type scattered symbolnum/value
00000008 False long False SUB False 1 (__TEXT,__text)
00000008 False long False UNSIGND False 1 (__TEXT,__text)
which is very similar to what is encoded when the symbols don't have the
leading 'L' and they are not temporary symbols. Which llvm-mc and the
Darwin assembler will encoded like this:
Relocation information (__TEXT,__text) 2 entries
address pcrel length extern type scattered symbolnum/value
00000008 False long True SUB False B
00000008 False long True UNSIGND False A
This is the missing relocation encoding needed to allow the Mach-O x86
Dwarf file and line table to be emitted. So this patch also removes the
TODO from the if() statement in MCMachOStreamer::Finish() that didn't
call MCDwarfFileTable::Emit() for 64-bit targets.
llvm-svn: 115389
LiveInterval::MergeValueNumberInto instead of trying to extend LiveRanges and
getting it wrong.
This fixed PR8249 where a valno with a multi-segment live range was defined by
an identity copy created by RemoveCopyByCommutingDef. Some of the live
segments disappeared.
llvm-svn: 115385
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
llvm-svn: 115364
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
Anyone interested in more general PRE would be better served by implementing it separately, to get real
anticipation calculation, etc.
llvm-svn: 115337
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
llvm-svn: 115243
use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.
llvm-svn: 115238
edited during emission.
If the basic block ends in a switch that gets lowered to a jump table, any
phis at the default edge were getting updated wrong. The jump table data
structure keeps a pointer to the header blocks that wasn't getting updated
after the MBB is split.
This bug was exposed on 32-bit Linux when disabling critical edge splitting in
codegen prepare.
The fix is to uipdate stale MBB pointers whenever a block is split during
emission.
llvm-svn: 115191
and output the dwarf line number tables. This contains the code to emit and
encode the dwarf line tables from the previously gathered information in the
MCLineSection objects. This contains all the details to encode the line and
address deltas into the dwarf line table.
To do this an MCDwarfLineAddrFragment has been added.
Also this moves the interface code out of Mach-O streamer into
MCDwarf so it should be useable by other object file formats.
There is now one call to be made from an MCObjectStreamer
EmitInstruction() method:
MCLineEntry::Make(this, getCurrentSection());
to create a line entry after each instruction is assembled.
And one call call to be made from an MCObjectStreamer Finish() method:
MCDwarfFileTable::Emit(this, DwarfLineSection);
when getContext().hasDwarfFiles() is true and is passed a object file specific
MCSection where to emit the dwarf file and the line tables.
This appears to now be correct for 32-bit targets, at least x86. But the
relocation entries for 64-bit Darwin needs some further work which is next
up to work on. So for now the 64-bit Mach-O target does not output the
dwarf file and line tables.
llvm-svn: 115157
if we are given a Layout object, even in cases when the value is not fixed.
This will be needed by the final patch for the dwarf .loc support to size a
new MCDwarf fragment needed to build and emit dwarf line number tables.
llvm-svn: 115155
With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
llvm-svn: 115134
resolved or not. Different object files have different restrictions and
different native assemblers have different idiosyncrasies we want to emulate
for now.
Move the existing MachO logic to the new place and implement an ELF one that
gets fixups to globals right.
llvm-svn: 115131
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
Anton Korobeynikov