Commit Graph

2 Commits

Author SHA1 Message Date
Alex Bradbury 96f3e7f221 [RISCV] Fix test/MC/Disassembler/RISCV/invalid-instruction.txt after rL347988
The test for [0x00 0x00] failed due to the introduction of c.unimp.

This particular test is unnecessary now that c.unimp was defined (and is 
tested in test/MC/RISCV/rv32c-valid.s).

llvm-svn: 348117
2018-12-03 10:35:46 +00:00
Ana Pazos b0799dda77 [RISCV] Fix decoding of invalid instruction with C extension enabled.
Summary:
The illegal instruction 0x00 0x00 is being wrongly decoded as
c.addi4spn with 0 immediate.

The invalid instruction 0x01 0x61 is being wrongly decoded as
c.addi16sp with 0 immediate.

This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer
for the RISC-V assembly language.

Reviewers: asb

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb

Differential Revision: https://reviews.llvm.org/D51815

llvm-svn: 342159
2018-09-13 18:21:19 +00:00