fcd29ae390
[fast-isel] Add support for returning non-legal types with no sign- or zero-
...
entend flag.
llvm-svn: 150774
2012-02-17 01:21:28 +00:00
a0d3c75015
Remove unnecessary assignment to temporary, ResultReg.
...
llvm-svn: 150737
2012-02-16 22:45:33 +00:00
0bc5132457
Add braces to if clause to make symmetric with associate else clause.
...
llvm-svn: 150591
2012-02-15 17:36:21 +00:00
dccc4794e6
Use a temporary variable, rather then a series of redundant calls.
...
llvm-svn: 150536
2012-02-15 00:23:55 +00:00
5b9c3974d2
Remove unnecessary assignment to temporary, ResultReg.
...
llvm-svn: 150520
2012-02-14 22:29:48 +00:00
0ee8c513f7
[fast-isel] Add support for SUBs with non-legal types.
...
llvm-svn: 150047
2012-02-08 02:45:44 +00:00
bd471255a9
[fast-isel] Add support for ORs with non-legal types.
...
llvm-svn: 150045
2012-02-08 02:29:21 +00:00
ded4c99f2e
[fast-isel] Add support for indirect branches.
...
llvm-svn: 150014
2012-02-07 23:56:08 +00:00
e55c556a24
Convert assert(0) to llvm_unreachable
...
llvm-svn: 149961
2012-02-07 02:50:20 +00:00
685b20c114
[fast-isel] Add support for ADDs with non-legal types.
...
llvm-svn: 149934
2012-02-06 23:50:07 +00:00
ae22c60f90
Persuade GCC that there is nothing worth warning about here (there isn't).
...
llvm-svn: 149834
2012-02-05 14:20:11 +00:00
b84a4b4c64
[fast-isel] Add support for URem.
...
llvm-svn: 149716
2012-02-03 21:23:45 +00:00
e023d5d7f3
[fast-isel] Rename isZExt to isSigned. No functional change intended.
...
llvm-svn: 149714
2012-02-03 21:14:11 +00:00
aaa55a88b6
[fast-isel] Add support for UDIV.
...
llvm-svn: 149712
2012-02-03 21:07:27 +00:00
41f0e78b6c
[fast-isel] Add support for FPToUI. Also add test cases for FPToSI.
...
llvm-svn: 149706
2012-02-03 20:27:51 +00:00
a8a8ac5d47
[fast-isel] Add support for selecting UIToFP.
...
llvm-svn: 149704
2012-02-03 19:42:52 +00:00
46a9f016c5
More dead code removal (using -Wunreachable-code)
...
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
d284c1d80d
Fix assert.
...
llvm-svn: 147966
2012-01-11 20:55:27 +00:00
083dbdca7f
Match SelectionDAG logic for enabling movt.
...
Darwin doesn't do static, and ELF targets only support static.
llvm-svn: 147740
2012-01-07 20:49:15 +00:00
8cdce7e690
Use getRegForValue() to materialize the address of ARM globals.
...
This enables basic local CSE, giving us 20% smaller code for
consumer-typeset in -O0 builds.
<rdar://problem/10658692>
llvm-svn: 147720
2012-01-07 04:07:22 +00:00
68f034ee1a
Use movw+movt in ARMFastISel::ARMMaterializeGV.
...
This eliminates a lot of constant pool entries for -O0 builds of code
with many global variable accesses.
This speeds up -O0 codegen of consumer-typeset by 2x because the
constant island pass no longer has to look at thousands of constant pool
entries.
<rdar://problem/10629774>
llvm-svn: 147712
2012-01-07 01:47:05 +00:00
68132d8093
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
...
llvm-svn: 146981
2011-12-20 18:26:50 +00:00
ded6160473
VFP2 is required for FP loads. Noticed by inspection.
...
llvm-svn: 146569
2011-12-14 17:55:03 +00:00
fce28914ea
Tidy up.
...
llvm-svn: 146568
2011-12-14 17:32:02 +00:00
a26979be29
Fix 80-column violation and extraneous brackets.
...
llvm-svn: 146566
2011-12-14 17:26:05 +00:00
7fae11b231
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
...
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
llvm-svn: 146542
2011-12-14 02:11:42 +00:00
563de603f7
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
...
load and then move the result from a GPR to a FPR.
llvm-svn: 146502
2011-12-13 19:22:14 +00:00
7f8e563a69
Add bundle aware API for querying instruction properties and switch the code
...
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
llvm-svn: 146026
2011-12-07 07:15:52 +00:00
c77830d21e
[arm-fast-isel] Doublewords only require word-alignment.
...
rdar://10528060
llvm-svn: 145891
2011-12-06 01:44:17 +00:00
80381f6cbf
Fix 80-column issues.
...
llvm-svn: 145783
2011-12-04 00:52:23 +00:00
ec3b77e00d
[arm-fast-isel] Unaligned stores of floats require special care.
...
rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
50f02cb21b
Move global variables in TargetMachine into new TargetOptions class. As an API
...
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
llvm-svn: 145714
2011-12-02 22:16:29 +00:00
9fd0e55e91
[arm-fast-isel] After promoting a function parameter be sure to update the
...
argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
llvm-svn: 145701
2011-12-02 20:25:18 +00:00
12330650f8
Silence wrong warnings from GCC about variables possibly being used
...
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.
llvm-svn: 145239
2011-11-28 10:31:27 +00:00
ee93ff736a
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
...
llvm-svn: 144959
2011-11-18 01:17:34 +00:00
0eff3e5c21
Add TODO comment.
...
llvm-svn: 144920
2011-11-17 21:46:13 +00:00
15b2498e88
Dead code.
...
llvm-svn: 144888
2011-11-17 07:24:49 +00:00
ce619ddfc5
Don't unconditionally set the kill flag.
...
rdar://10456186
llvm-svn: 144872
2011-11-17 01:16:53 +00:00
80979b6ea6
Check to make sure we can select the instruction before trying to put the
...
operands into a register. Otherwise, we may materialize dead code.
llvm-svn: 144805
2011-11-16 18:39:44 +00:00
af13d767a2
Add FIXME comment.
...
llvm-svn: 144743
2011-11-16 00:32:20 +00:00
0745e645e0
Remove some unnecessary includes of PseudoSourceValue.h.
...
llvm-svn: 144631
2011-11-15 07:24:32 +00:00
057b6d3476
Supporting inline memmove isn't going to be worthwhile. The only way to avoid
...
violating a dependency is to emit all loads prior to stores. This would likely
cause a great deal of spillage offsetting any potential gains.
llvm-svn: 144585
2011-11-14 23:04:09 +00:00
ab7223e99a
Add support for inlining small memcpys.
...
rdar://10412592
llvm-svn: 144578
2011-11-14 22:46:17 +00:00
45110fdf8d
Fix a performance regression from r144565. Positive offsets were being lowered
...
into registers, rather then encoded directly in the load/store.
llvm-svn: 144576
2011-11-14 22:34:48 +00:00
adfd200bcb
Add support for Thumb load/stores with negative offsets.
...
rdar://10412592
llvm-svn: 144565
2011-11-14 20:22:27 +00:00
2a1df883d0
Add support for ARM halfword load/stores and signed byte loads with negative
...
offsets.
rdar://10412592
llvm-svn: 144518
2011-11-14 04:09:28 +00:00
1198d894d0
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
...
llvm-svn: 144494
2011-11-13 09:44:21 +00:00
a476e391f1
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
...
llvm-svn: 144492
2011-11-13 05:14:43 +00:00
5196efdf36
Fix comments.
...
llvm-svn: 144490
2011-11-13 04:25:02 +00:00
c8cfd3a8fb
Add support for emitting both signed- and zero-extend loads. Fix
...
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
llvm-svn: 144488
2011-11-13 02:23:59 +00:00
a7ebc5617d
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
...
llvm-svn: 144426
2011-11-11 23:31:03 +00:00
e19b0a9eb8
Rename variables to avoid confusion. No functionallity change intended.
...
llvm-svn: 144377
2011-11-11 06:27:41 +00:00
7ddd63ce4e
Add support for using immediates with select instructions.
...
rdar://10412592
llvm-svn: 144376
2011-11-11 06:20:39 +00:00
023ede5649
When loading a value, treat an i1 as an i8.
...
llvm-svn: 144356
2011-11-11 02:38:59 +00:00
2a3503e061
Add support for using MVN to materialize negative constants.
...
rdar://10412592
llvm-svn: 144348
2011-11-11 00:36:21 +00:00
d1762e00e2
When in ARM mode, LDRH/STRH require special handling of negative offsets.
...
For correctness, disable this for now.
rdar://10418009
llvm-svn: 144316
2011-11-10 21:09:49 +00:00
3fbd094ad9
For immediate encodings of icmp, zero or sign extend first. Then
...
determine if the value is negative and flip the sign accordingly.
rdar://10422026
llvm-svn: 144258
2011-11-10 01:30:39 +00:00
2f27fab6ed
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
...
rdar://10418009
llvm-svn: 144213
2011-11-09 21:30:12 +00:00
595d419427
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
...
remove a fair number of unnecessary materialized constants.
rdar://10412592
llvm-svn: 144163
2011-11-09 03:22:02 +00:00
0439cfc41f
ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
...
No functional change intended.
llvm-svn: 144122
2011-11-08 21:12:00 +00:00
5de1bea5c9
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
...
callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
llvm-svn: 144047
2011-11-08 00:03:32 +00:00
d0191a53c9
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
...
zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
llvm-svn: 143821
2011-11-05 20:16:15 +00:00
5b8fdd7b62
Cannot create a result register for non-legal types.
...
llvm-svn: 143749
2011-11-04 23:45:39 +00:00
e8b8b77307
When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit
...
in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend. This prevents us from materializing things
such as 'true' (i.e., i1 1).
llvm-svn: 143743
2011-11-04 23:09:49 +00:00
67f96887aa
Enable support for materializing i1, i8, and i16 integers via move immediate.
...
llvm-svn: 143739
2011-11-04 22:29:00 +00:00
8a98ec4d4b
Indentation.
...
llvm-svn: 143670
2011-11-04 00:58:10 +00:00
f3e73ad5da
Add fast-isel support for returning i1, i8, and i16.
...
llvm-svn: 143669
2011-11-04 00:50:21 +00:00
bf5f4bec1a
Add support for sign-extending non-legal types in SelectSIToFP().
...
llvm-svn: 143603
2011-11-03 02:04:59 +00:00
9cf803c4bf
Add support for comparing integer non-legal types.
...
llvm-svn: 143559
2011-11-02 18:08:25 +00:00
4489f948a7
Factor out an EmitIntExt function. No functionality change intended.
...
llvm-svn: 143547
2011-11-02 17:20:24 +00:00
ee7e452571
Factor out a SelectTrunc function. No functionality change intended.
...
llvm-svn: 143523
2011-11-02 00:18:48 +00:00
d24e7e1d9b
A branch predicated on a constant can just FastEmit an unconditional branch.
...
llvm-svn: 143086
2011-10-27 00:21:16 +00:00
a486f44733
Add a TODO comment. FastISel works by parsing each basic block from the bottom
...
up. Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle. This creates many more
opportunities for target specific fast-isel.
llvm-svn: 143079
2011-10-26 23:34:37 +00:00
78127d31f3
Factor a little more code into EmitCmp, which should have been done in the first
...
place. No functional change intended.
llvm-svn: 143078
2011-10-26 23:25:44 +00:00
eafbf3faa9
Use EmitCmp in SelectBranch. No functional change intended.
...
llvm-svn: 143076
2011-10-26 23:17:28 +00:00
59a201950b
Factor out an EmitCmp function that can be used by both SelectCmp and
...
SelectBranch. No functional change intended.
llvm-svn: 143072
2011-10-26 22:47:55 +00:00
b522550ce5
Add a few FIXME comments.
...
llvm-svn: 142299
2011-10-17 22:54:23 +00:00
7753d66468
Switch over to using ARMConstantPoolConstant for global variables, functions,
...
and block addresses.
llvm-svn: 140936
2011-10-01 08:00:54 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
...
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
e7e2aca322
Tidy up a few 80 column violations.
...
llvm-svn: 139636
2011-09-13 20:30:37 +00:00
f3dd6da7a8
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
...
llvm-svn: 139044
2011-09-02 22:33:24 +00:00
17847ae757
Fixup for functions that return a bool.
...
llvm-svn: 138918
2011-08-31 23:49:05 +00:00
50b0f6669c
[SU]XT[BH] are only available on ARMv6 and up.
...
llvm-svn: 138373
2011-08-23 20:53:08 +00:00
8b31ef50c0
ARM extend instructions simplification.
...
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.
llvm-svn: 136225
2011-07-27 16:47:19 +00:00
a20cde31e7
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
...
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
229907cd11
land David Blaikie's patch to de-constify Type, with a few tweaks.
...
llvm-svn: 135375
2011-07-18 04:54:35 +00:00
194c3dc01f
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
...
llvm-svn: 134030
2011-06-28 21:14:33 +00:00
6cc775f905
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
...
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
llvm-svn: 134021
2011-06-28 19:10:37 +00:00
0713a9d8fc
Add a parameter to CCState so that it can access the MachineFunction.
...
No functional change.
Part of PR6965
llvm-svn: 132763
2011-06-08 23:55:35 +00:00
86585798af
Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.
...
rdar://9431157
llvm-svn: 132522
2011-06-03 01:13:19 +00:00
6528a54946
Fix ARM fast isel to correctly flag memory operands to stores. This fixes
...
-verify-machineinstrs failures on several tests.
llvm-svn: 132268
2011-05-28 20:34:49 +00:00
fe84bd659c
Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076
...
llvm-svn: 132194
2011-05-27 18:02:04 +00:00
c70355195c
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
...
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
llvm-svn: 132099
2011-05-25 23:49:02 +00:00
5bbb75655b
Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for i8 and i16 values.
...
llvm-svn: 132073
2011-05-25 19:09:45 +00:00
4e983166bc
Kill some dead code.
...
llvm-svn: 131431
2011-05-16 22:24:07 +00:00
39b56b4b9f
Apparently the check for direct calls is unnecessary.
...
llvm-svn: 130716
2011-05-02 20:16:33 +00:00
328bad02fa
Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns.
...
llvm-svn: 130552
2011-04-29 22:48:03 +00:00
7708746c33
Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but
...
if it ever did it needs the def machinery.
llvm-svn: 130549
2011-04-29 22:07:50 +00:00
26b8ac4b8c
Some cleanup and optimize fallthrough more.
...
llvm-svn: 130546
2011-04-29 21:56:31 +00:00
86caced370
Re-committing r130454, which does not in fact break anything.
...
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .
llvm-svn: 130539
2011-04-29 21:22:56 +00:00
8d46b47787
Add trunc->branch support, this won't help with clang's i8->i1 truncations
...
for bools, but is a start.
llvm-svn: 130534
2011-04-29 20:02:39 +00:00
9ade5e2495
Update comments and checks to match reality.
...
llvm-svn: 130464
2011-04-29 00:07:20 +00:00
501d2e2c14
Whitespace.
...
llvm-svn: 130463
2011-04-29 00:03:10 +00:00
517728b1ae
Revert r130454; apparently this doesn't actually work.
...
llvm-svn: 130462
2011-04-28 23:55:14 +00:00
e4ecd42926
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
...
rdar://problem/9338332 .
llvm-svn: 130454
2011-04-28 23:03:25 +00:00
4f012fd0a1
Be more layout aware here and swap the successor and branch condition
...
if it means we get a fallthrough.
llvm-svn: 130404
2011-04-28 16:52:09 +00:00
ebddfe60a0
Correct result when a branch condition is live across a block
...
boundary. <rdar://problem/8933028>
llvm-svn: 129634
2011-04-16 03:31:26 +00:00
7c14a558fe
Don't include Operator.h from InstrTypes.h.
...
llvm-svn: 129271
2011-04-11 09:35:34 +00:00
b968f4defe
Just use BL all the time. It's safer that way.
...
Fixes rdar://9184526
llvm-svn: 128869
2011-04-05 00:39:26 +00:00
53dd03d537
Add a ARM-specific SD node for VBSL so that forms with a constant first operand
...
can be recognized. This fixes <rdar://problem/9183078>.
llvm-svn: 128584
2011-03-30 23:01:21 +00:00
a5a779ef45
Migrate the fix in r128041 to ARM's fastisel support as well.
...
Fixes rdar://9169640
llvm-svn: 128100
2011-03-22 19:39:17 +00:00
174d872702
Sometimes isPredicable lies to us and tells us we don't need the operands.
...
Go ahead and add them on when we might want to use them and let
later passes remove them.
Fixes rdar://9118569
llvm-svn: 127518
2011-03-12 01:09:29 +00:00
919772fd5d
Only use blx for external function calls on thumb, these could be fixed
...
up by the dynamic linker, but it's better to use the correct instruction
to begin with.
Fixes rdar://9011034
llvm-svn: 126176
2011-02-22 01:37:10 +00:00
331cc5218d
Use the incoming VT not the VT of where we're trying to store to determine
...
if we can store a value. Also, the exclusion is or, not and.
Fixes rdar://8920247.
llvm-svn: 124357
2011-01-27 05:44:56 +00:00
249fcd4499
Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.
...
llvm-svn: 123707
2011-01-18 00:51:23 +00:00
dfce83c8f5
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
...
movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0
It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.
llvm-svn: 123619
2011-01-17 08:03:18 +00:00
1b3f5b9f74
fix some -Wself-assign warnings.
...
llvm-svn: 122893
2011-01-05 18:41:05 +00:00
c874f6c9ff
Arm and thumb call instructions are also in different orders.
...
Fixes rdar://8782223
llvm-svn: 122313
2010-12-21 03:50:43 +00:00
347f4c32e8
Don't handle -arm-long-calls in fast isel for now.
...
llvm-svn: 121919
2010-12-15 23:47:29 +00:00
119ff7ff04
Refactor load/store handling again. Simplify and make some room for
...
reg+reg handling.
llvm-svn: 120526
2010-12-01 01:40:24 +00:00
78b4efb472
Noticed this on inspection, fix and update some comments.
...
llvm-svn: 120447
2010-11-30 19:14:07 +00:00
43b0c6d94f
Update fastisel for the changes in r120272.
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llvm-svn: 120324
2010-11-29 21:56:23 +00:00
527da1b6e2
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
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llvm-svn: 119990
2010-11-23 03:31:01 +00:00
0a3c28bd6b
Rewrite address handling to use a structure with all the possible address
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mode variables. Handle frame indexes in load/store and allocas again.
llvm-svn: 119912
2010-11-20 22:38:27 +00:00
d0aec3bf64
STRH only needs the additional operand, not t2STRH. Also invert conditional
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to match the one from the load emitter above.
llvm-svn: 119911
2010-11-20 22:01:38 +00:00
35e2d7f610
Don't need to save piecemeal now.
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llvm-svn: 119862
2010-11-19 22:39:56 +00:00
cee83d6e6b
Update comment.
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llvm-svn: 119861
2010-11-19 22:37:58 +00:00
558b61e2d4
Update comment.
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llvm-svn: 119859
2010-11-19 22:36:41 +00:00
fef5f315af
Refactor address mode handling into a single struct (ala x86), this
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should give allow a wider range of addressing modes.
No functional change.
llvm-svn: 119856
2010-11-19 22:30:02 +00:00
d7a3550a5e
Remove hard tabs.
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llvm-svn: 119810
2010-11-19 18:01:37 +00:00
964943780b
Recommit this change and remove the failing part of the test - it didn't
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pass in the first place and was masked by earlier failures not warning
and aborting the block.
llvm-svn: 119184
2010-11-15 21:11:06 +00:00
1293c6a23a
Temporarily revert this.
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llvm-svn: 118946
2010-11-12 23:50:48 +00:00
49a66f7d71
Make this happen for ARM like x86. Don't entirely bail out when
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an address is in a different block, get it into a register and go
from there.
llvm-svn: 118936
2010-11-12 22:52:32 +00:00
22d0492f34
Fix up a few more spots of addrmode2 (or not) changes that were
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missed. Update some comments accordingly.
Fixes rdar://8652289
llvm-svn: 118888
2010-11-12 09:48:30 +00:00
68147ee320
Trailing whitespace.
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llvm-svn: 118606
2010-11-09 19:22:26 +00:00
89965d7091
Make sure we have movw on the target before using it.
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Fixes 8559.
llvm-svn: 118333
2010-11-06 07:53:11 +00:00
71049f78ed
In the calling convention logic, ValVT is always a legal type,
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and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
llvm-svn: 118245
2010-11-04 10:49:57 +00:00
e4dd7378d0
Optimize generated code for integer materialization a bit.
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llvm-svn: 118192
2010-11-03 20:21:17 +00:00
1462777017
Simplify uses of MVT and EVT. An MVT can be compared directly
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with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
llvm-svn: 118169
2010-11-03 12:17:33 +00:00
f5dda01f33
Inside the calling convention logic LocVT is always a simple
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value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
c63d846ad6
Invert these branches by default, it makes assembly comparisons a little
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easier to read.
llvm-svn: 118148
2010-11-03 04:29:11 +00:00
1e43892e4b
Make sure we're only storing a single bit here.
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llvm-svn: 118126
2010-11-02 23:59:09 +00:00
b2abb508ae
Remove an assert - it's possible to be hit, and we just want to avoid
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handling those cases for now.
llvm-svn: 117996
2010-11-02 01:24:49 +00:00
ac746e1b38
Whitespeace
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llvm-svn: 117995
2010-11-02 01:22:45 +00:00
e8fccc82e4
No really, no thumb1 for arm fast isel. Also add an informative comment as
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to what someone would need to do to support thumb1.
llvm-svn: 117994
2010-11-02 01:21:28 +00:00
04b0a3e651
Make sure we have a legal type (and simple) before continuing.
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llvm-svn: 117848
2010-10-30 21:25:26 +00:00
5c308f8452
Handle comparison values we already have - this fixes the consumer-typeset
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failure for llvm-gcc on arm fast isel.
llvm-svn: 117710
2010-10-29 21:08:19 +00:00
338de3ee56
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
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the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
055de2c789
Trailing whitespace
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llvm-svn: 117496
2010-10-27 21:39:08 +00:00
5a7c715470
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
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rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
Chad Rosier