Commit Graph

101 Commits

Author SHA1 Message Date
Krzysztof Parzyszek 545a68ca4b [Hexagon] Add instruction definitions for Hexagon V66
llvm-svn: 348411
2018-12-05 21:01:07 +00:00
Fangrui Song 5093b41d8a [MC] Fix 3 objdump tests after rL346610
llvm-svn: 346617
2018-11-11 19:15:27 +00:00
Krzysztof Parzyszek f740fd647a [Hexagon] Handle Hexagon's SHF_HEX_GPREL section flag
llvm-svn: 346494
2018-11-09 14:17:27 +00:00
Krzysztof Parzyszek 6bfc6577f2 [Hexagon] Remove support for V4
llvm-svn: 344791
2018-10-19 17:31:11 +00:00
Sid Manning 8d4a6615e1 Check for tied operands
Differential Revision: https://reviews.llvm.org/D50592

llvm-svn: 339567
2018-08-13 14:01:25 +00:00
Krzysztof Parzyszek 03aa8f3a24 [Hexagon] Fix the value of HexagonII::TypeCVI_FIRST
This value is the first vector instruction type in numerical order. The
previous value was incorrect, leaving TypeCVI_GATHER outside of the range
for vector instructions. This caused vector .new instructions to be
incorrectly encoded in the presence of gather.

llvm-svn: 335065
2018-06-19 18:09:54 +00:00
Alex Bradbury 5e41fc83c5 [Hexagon] Use addAliasForDirective for data directives
Data directives such as .word, .half, .hword are currently parsed using 
HexagonAsmParser::ParseDirectiveValue which effectively duplicates logic from 
AsmParser::parseDirectiveValue. This patch deletes that duplicated logic in 
favour of using addAliasForDirective.

Differential Revision: https://reviews.llvm.org/D46999

llvm-svn: 332607
2018-05-17 13:21:18 +00:00
Sid Manning d9f2873511 Hexagon: Put relocations after instructions not packets.
Change relocation output so that relocation information follows
individual instructions rather than clustering them at the end
of packets.

This change required shifting block of code but the actual change
is in HexagonPrettyPrinter's PrintInst.

Differential Revision: https://reviews.llvm.org/D46728

llvm-svn: 332283
2018-05-14 19:46:08 +00:00
Krzysztof Parzyszek 786fc3d079 [Hexagon] Move clamping of extended operands directly to MC code emitter
llvm-svn: 331653
2018-05-07 17:34:23 +00:00
Krzysztof Parzyszek 4f99836a9e [Hexagon] Recognize and handle :endloop01
llvm-svn: 328870
2018-03-30 15:29:47 +00:00
Krzysztof Parzyszek 5f7ba9a74c [Hexagon] Always generate mux out of predicated transfers if possible
HexagonGenMux would collapse pairs of predicated transfers if it assumed
that the predicated .new forms cannot be created. Turns out that generating
mux is preferable in almost all cases.
Introduce an option -hexagon-gen-mux-threshold that controls the minimum
distance between the instruction defining the predicate and the later of
the two transfers. If the distance is closer than the threshold, mux will
not be generated. Set the threshold to 0 by default.

llvm-svn: 328346
2018-03-23 18:43:09 +00:00
Krzysztof Parzyszek c5e0ed109d [Hexagon] Add trap1 instruction
llvm-svn: 326492
2018-03-01 21:54:08 +00:00
Krzysztof Parzyszek 22a21d4c5d [Hexagon] Add guest registers
llvm-svn: 326450
2018-03-01 17:03:26 +00:00
Krzysztof Parzyszek 7cfe7cbccc [Hexagon] Express calling conventions via .td file instead of hand-coding
Additionally, simplify the rest of the argument/parameter lowering code.

llvm-svn: 324737
2018-02-09 15:30:02 +00:00
Krzysztof Parzyszek a8ab1b75cb [Hexagon] Add support for Hexagon V65
llvm-svn: 320404
2017-12-11 18:57:54 +00:00
Krzysztof Parzyszek 6acecc96ac [Hexagon] Remove trailing spaces, NFC
llvm-svn: 318875
2017-11-22 20:43:00 +00:00
Sumanth Gundapaneni e1983bcf55 [Hexagon] New HVX target features.
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"

For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"

Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.

Differential Revision: https://reviews.llvm.org/D38851

llvm-svn: 316101
2017-10-18 18:07:07 +00:00
Krzysztof Parzyszek f63ad39e7d [Hexagon] Handle a global operand to A2_addi when creating duplexes
llvm-svn: 306012
2017-06-22 15:53:31 +00:00
Krzysztof Parzyszek 57a8bb4343 [Hexagon] Change iconst to emit 27bit relocation
Patch by Colin LeMahieu.

llvm-svn: 301956
2017-05-02 18:19:11 +00:00
Krzysztof Parzyszek a750383d0f [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCREL
Patch by Sid Manning.

llvm-svn: 301955
2017-05-02 18:15:33 +00:00
Krzysztof Parzyszek b0af1ef741 [Hexagon] Make sure duplexed dealloc_returns are checked for double jumps
Patch by Colin LeMahieu.

llvm-svn: 301951
2017-05-02 18:03:08 +00:00
Krzysztof Parzyszek 49f7e0a98b [Hexagon] Move checking AXOK to checker
Patch by Colin LeMahieu.

llvm-svn: 301949
2017-05-02 18:00:37 +00:00
Krzysztof Parzyszek c15f8d2a08 [Hexagon] Extract function that checks endloops with other branches
Change location number to point to conflicting branch instruction.

Patch by Colin LeMahieu.

llvm-svn: 301946
2017-05-02 17:56:11 +00:00
Krzysztof Parzyszek 55db483a46 [Hexagon] Improving error reporting for writing to read only registers
Patch by Colin LeMahieu.

llvm-svn: 301828
2017-05-01 20:10:41 +00:00
Krzysztof Parzyszek e96d27a997 [Hexagon] Give better error messages for solo instruction errors
Patch by Colin LeMahieu.

llvm-svn: 301827
2017-05-01 20:06:01 +00:00
Colin LeMahieu 553ec588ae [Hexagon] Fixing test from 297920 to add Hexagon triple.
llvm-svn: 297926
2017-03-16 01:52:10 +00:00
Colin LeMahieu ddebad956e [Hexagon] Updating inline saturate lanes for v62 version.
llvm-svn: 297920
2017-03-16 00:35:28 +00:00
Krzysztof Parzyszek 5f4dedffd4 [Hexagon] Fix testcase accidentally broken by r296645
llvm-svn: 296647
2017-03-01 17:53:42 +00:00
Krzysztof Parzyszek f9015e62fd [Hexagon] Introduce Hexagon V62
llvm-svn: 294805
2017-02-10 23:46:45 +00:00
Krzysztof Parzyszek a72fad980c [Hexagon] Replace instruction definitions with auto-generated ones
llvm-svn: 294753
2017-02-10 15:33:13 +00:00
Krzysztof Parzyszek c8d676ef72 [Hexagon] Remove encoding bits from mapped instructions
- Map A2_zxtb to A2_andir.
- Map PS_call_nr J2_call.
- Map A2_tfr[t|f][new] to A2_padd[t|f][new].
    
Patch by Colin LeMahieu.

llvm-svn: 294320
2017-02-07 17:42:11 +00:00
Krzysztof Parzyszek 5b4a6b67c5 [Hexagon] Adding gp+ to the syntax of gp-relative instructions
Patch by Colin LeMahieu.

llvm-svn: 294258
2017-02-06 23:18:57 +00:00
Krzysztof Parzyszek 8cdfe8ecf3 [Hexagon] Update MCTargetDesc
Changes include:
- Updates to the instruction descriptor flags.
- Improvements to the packet shuffler and checker.
- Updates to the handling of certain relocations.
- Better handling of duplex instructions.

llvm-svn: 294226
2017-02-06 19:35:46 +00:00
Krzysztof Parzyszek d0d42f0ec8 [Hexagon] Adding opExtentBits and opExtentAlign to GPrel instructions
Patch by Colin LeMahieu.

llvm-svn: 293933
2017-02-02 20:35:12 +00:00
Krzysztof Parzyszek e17b0bfb24 [Hexagon] Fix relocation kind for extended predicated calls
Patch by Sid Manning.

llvm-svn: 293931
2017-02-02 20:21:56 +00:00
Krzysztof Parzyszek 73e0ad8220 [Hexagon] Fix disassembler crash after r279255
When p0 was added as an explicit operand to the duplex subinstructions,
the disassembler was not updated to reflect this.

llvm-svn: 281104
2016-09-09 21:45:00 +00:00
Daniel Sanders 8e3c74210f Remove redundant -mattr options from llvm-objdump commands.
The -mattr options in these four tests have no effect on the output of
llvm-objdump. In the case of the two Mips tests, removing the -mattr option
left duplicate RUN lines so the duplicates have been removed.

llvm-svn: 272906
2016-06-16 15:47:19 +00:00
Krzysztof Parzyszek a053101c95 [Hexagon] Use pipe instead of temporary files in tests
llvm-svn: 270217
2016-05-20 14:01:34 +00:00
Krzysztof Parzyszek 7c7bb538cb [Hexagon] Treat all conditional branches as predicted (not-taken by default)
llvm-svn: 268946
2016-05-09 18:22:07 +00:00
Krzysztof Parzyszek f7a4bd4068 [Hexagon] Add aliases for vector loads/stores with no explicit offset
The mem(r0) instructions are treated as mem(r0+#0).

llvm-svn: 268661
2016-05-05 18:38:35 +00:00
Krzysztof Parzyszek e5fcce2d2b [Hexagon] Add instruction aliases for vector unsigned compare-equal
Unsigned compare-equal instructions are mapped to signed compare-equal.

llvm-svn: 267925
2016-04-28 19:49:18 +00:00
Krzysztof Parzyszek 0e7d2d339d [Hexagon] Define certain aliases for vector instructions
Specifically:
  Vd = #0   -> Vd = vxor(Vd, Vd)
  Vdd = #0  -> Vdd.w = vsub(Vdd.w, Vdd.w)
  Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L)

llvm-svn: 267901
2016-04-28 16:43:16 +00:00
Krzysztof Parzyszek e737b86f8c [Hexagon] Handle double-vector registers as new-value producers
Patch by Colin LeMahieu.

llvm-svn: 267897
2016-04-28 15:54:48 +00:00
Colin LeMahieu a3782da3e3 [Hexagon] Merging nops in to previous packet rather than always creating a new one.
llvm-svn: 267798
2016-04-27 21:37:44 +00:00
Krzysztof Parzyszek a4602b5be1 [Hexagon] Use llvm-mc instead of llc in an MC testcase
Remember to svn add the new file.

llvm-svn: 267435
2016-04-25 18:09:36 +00:00
Krzysztof Parzyszek 4ea9bd72df [Hexagon] Use llvm-mc instead of llc in an MC testcase
llvm-svn: 267434
2016-04-25 18:08:33 +00:00
Krzysztof Parzyszek e6ee481bdf [Hexagon] Correctly set "Flags" in ELF header
llvm-svn: 267397
2016-04-25 12:49:47 +00:00
Krzysztof Parzyszek e2c6405708 [Hexagon] Add definitions for trap/pause instructions
Also add tests for other instructions from HexagonSystemInst.td.

llvm-svn: 267162
2016-04-22 16:25:00 +00:00
Krzysztof Parzyszek adf02ae540 [Hexagon] Properly recognize register alt names
llvm-svn: 267038
2016-04-21 19:49:53 +00:00
Krzysztof Parzyszek 5626703837 [Hexagon] Fix handling of lcomm directive
Patch by Colin LeMahieu.

llvm-svn: 266882
2016-04-20 15:54:13 +00:00