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111 Commits

Author SHA1 Message Date
Chris Lattner bb1c9ecb17 simplify this code using the new regclass info passed in 
llvm-svn: 23557
 2005-09-30 17:12:38 +00:00
Chris Lattner a654525c1c Pass extra regclasses into spilling code 
llvm-svn: 23537
 2005-09-30 01:29:42 +00:00
Chris Lattner de3c87a2ab Implement the isLoadFromStackSlot interface 
llvm-svn: 23387
 2005-09-19 05:23:44 +00:00
Chris Lattner 8ad3700a3e The simple isel being gone makes this dead! 
llvm-svn: 22914
 2005-08-19 18:32:03 +00:00
Jeff Cohen 5f4ef3c5a8 Eliminate all remaining tabs and trailing spaces. 
llvm-svn: 22523
 2005-07-27 06:12:32 +00:00
Nate Begeman 8a0933608a First round of support for doing scalar FP using the SSE2 ISA extension and 
XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

llvm-svn: 22340
 2005-07-06 18:59:04 +00:00
Chris Lattner 97e3b65652 Teach reginfo how to deal with ADJSTACKPTRri, allowing us to generate: 
add %ESP, 20
        jmp %EDX  # TAIL CALL

instead of:
        add %ESP, -8
        add %ESP, 28
        jmp %EDX  # TAIL CALL

llvm-svn: 22047
 2005-05-15 05:49:58 +00:00
Chris Lattner 5366c859a7 When emitting the function epilog, check to see if there already a stack 
adjustment.  If so, we merge the adjustment into the existing one.  This
allows us to generate:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        add %ESP, 8
        ret 4

intead of:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        sub %ESP, 4
        add %ESP, 12
        ret 4

for X86/fast-cc-merge-stack-adj.ll

llvm-svn: 22038
 2005-05-14 23:53:43 +00:00
Chris Lattner f0649db870 Add some new instructions 
llvm-svn: 22036
 2005-05-14 23:35:21 +00:00
Chris Lattner c0e369ed66 switch to having the callee pop stack operands for fastcc. This is currently buggy 
do not use

llvm-svn: 21984
 2005-05-13 21:44:04 +00:00
Chris Lattner 1a12476531 allow RETI 
llvm-svn: 21980
 2005-05-13 20:46:35 +00:00
Chris Lattner c21db6b15c add signed versions of the extra precision multiplies 
llvm-svn: 21106
 2005-04-06 04:19:22 +00:00
Chris Lattner 0edf9535b9 Add rotate instructions. 
llvm-svn: 19690
 2005-01-19 07:50:03 +00:00
Chris Lattner d54845f530 Improve coverage of the X86 instruction set by adding 16-bit shift doubles. 
llvm-svn: 19687
 2005-01-19 07:31:24 +00:00
Chris Lattner 5b589ec0c4 Add conditional moves for the parity flag. 
llvm-svn: 19437
 2005-01-10 22:09:33 +00:00
Chris Lattner b62b45b3fc Add support for SETNPr to lower to memory form. 
llvm-svn: 19248
 2005-01-02 02:37:46 +00:00
Chris Lattner 33660426a5 Spill/restore X86 floating point stack registers with 64-bits of precision 
instead of 80-bits of precision.  This fixes PR467.

This change speeds up fldry on X86 with LLC from 7.32s on apoc to 4.68s.

llvm-svn: 18433
 2004-12-02 18:17:31 +00:00
Chris Lattner e9bfa5a2a4 Add some new instructions. Fix the asm string for sbb32rr 
llvm-svn: 16759
 2004-10-06 04:01:02 +00:00
Reid Spencer 7c16caa336 Changes For Bug 352 
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.

llvm-svn: 16137
 2004-09-01 22:55:40 +00:00
Chris Lattner 7c98308013 Reduce uses of getRegClass 
llvm-svn: 15973
 2004-08-21 20:13:52 +00:00
Chris Lattner a0b38d3cb1 Code insertion methods now return void instead of an int. 
llvm-svn: 15780
 2004-08-15 22:15:11 +00:00
Chris Lattner 98de1d7795 These methods no longer take a TargetRegisterClass* operand. 
llvm-svn: 15774
 2004-08-15 21:56:44 +00:00
Nate Begeman a4da0d6294 Eliminate MachineFunction& argument from eliminateFrameIndex in x86 Target. Get MachineFunction from MachineInstruction's parent's parent 
llvm-svn: 15739
 2004-08-14 22:05:10 +00:00
Chris Lattner 8a4039ed9a Reserve the correct amt of space. 
llvm-svn: 14913
 2004-07-17 20:24:05 +00:00
Chris Lattner c2726e63ed Delete the allocate*TargetMachine function, which is now dead . 
The shared command line options are now in a header that makes sense.

llvm-svn: 14756
 2004-07-11 04:17:10 +00:00
Reid Spencer eb04d9bcb4 Add #include <iostream> since Value.h does not #include it any more. 
llvm-svn: 14622
 2004-07-04 12:19:56 +00:00
Misha Brukman c22299d21b Spell out `NoFramePointerElim' for readability. 
llvm-svn: 14299
 2004-06-21 21:17:44 +00:00
Misha Brukman 5cb198a9c6 Use the common `NoFPElim' setting instead of our own. 
llvm-svn: 14298
 2004-06-21 21:10:24 +00:00
Chris Lattner 6b7275996c Rename Type::PrimitiveID to TypeId and ::getPrimitiveID() to ::getTypeID() 
llvm-svn: 14201
 2004-06-17 18:19:28 +00:00
Chris Lattner a0cfedef3a Add support for the setp instructions 
llvm-svn: 14140
 2004-06-11 04:30:06 +00:00
Chris Lattner 82baa9c394 Convert to the new TargetMachine interface. 
llvm-svn: 13952
 2004-06-02 05:55:25 +00:00
Alkis Evlogimenos d186ed02e4 Add more ADC and SBB variants 
llvm-svn: 12607
 2004-04-02 07:11:10 +00:00
Chris Lattner 358c97e7ae Implement spill code folding for all of the conditional move instructions 
llvm-svn: 12554
 2004-03-30 21:29:47 +00:00
Alkis Evlogimenos 4837f6c0d9 Another API change to MRegisterInfo::foldMemoryOperand. Instead of a 
MachineBasicBlock::iterator take a MachineInstr*.

llvm-svn: 12392
 2004-03-14 20:14:27 +00:00
Alkis Evlogimenos 48da2f8a6d Change MRegisterInfo::foldMemoryOperand to return the folded 
instruction to make the API more flexible.

llvm-svn: 12386
 2004-03-14 07:19:51 +00:00
Alkis Evlogimenos d6f62ba55b Add memory operand version of conditional move. 
llvm-svn: 12190
 2004-03-07 03:19:11 +00:00
Alkis Evlogimenos ea81b79a97 A big X86 instruction rename. The instructions are renamed to make 
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995
 2004-02-29 08:50:03 +00:00
Alkis Evlogimenos fa63580517 SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them 
to denote this fact.

llvm-svn: 11972
 2004-02-28 23:46:44 +00:00
Alkis Evlogimenos 4953ae085a Floating point loads/stores act on memory operands. Rename them to 
denote this fact.

llvm-svn: 11971
 2004-02-28 23:42:35 +00:00
Alkis Evlogimenos 5b5dee4afb Uncomment instructions that take both an immediate and a memory 
operand but their sizes differ.

llvm-svn: 11969
 2004-02-28 22:06:59 +00:00
Alkis Evlogimenos 2debead504 Do not generate instructions with mismatched memory/immediate sized 
operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944
 2004-02-28 06:01:43 +00:00
Alkis Evlogimenos 9476b7cbe5 Add memory operand folding support for the SETcc family of 
instructions.

llvm-svn: 11907
 2004-02-27 16:13:37 +00:00
Alkis Evlogimenos 8d99063b38 Add memory operand folding support for SHLD and SHRD instructions. 
llvm-svn: 11905
 2004-02-27 15:03:18 +00:00
Alkis Evlogimenos 3537404299 Add memory operand folding support for SHL, SHR and SAR, SHLD instructions. 
llvm-svn: 11903
 2004-02-27 09:28:43 +00:00
Alkis Evlogimenos 8358cc573d Move MOTy::UseType enum into MachineOperand. This eliminates the 
switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).

llvm-svn: 11715
 2004-02-22 19:23:26 +00:00
Alkis Evlogimenos de51c65299 When folding memory operands in machine instructions be careful to 
leave register operands with the same use/def flags as the original
instruction.

llvm-svn: 11709
 2004-02-22 06:54:26 +00:00
Chris Lattner 30e73e3442 Add support for GlobalAddress's for alkis 
llvm-svn: 11560
 2004-02-17 18:23:55 +00:00
Alkis Evlogimenos cf7b9392ea Instructiosn with 1 memory operand have 4 operands in our 
representation.. duh!

llvm-svn: 11554
 2004-02-17 15:58:13 +00:00
Alkis Evlogimenos f90da5f346 Align case statements. 
llvm-svn: 11552
 2004-02-17 15:50:41 +00:00
Alkis Evlogimenos 546513ccfd Add TEST and XCHG memory operand support. 
llvm-svn: 11550
 2004-02-17 15:48:42 +00:00