9fee442e63
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
...
llvm-svn: 28324
2006-05-16 07:21:53 +00:00
aa10fb7ebe
Make this print the right start pointer
...
llvm-svn: 28321
2006-05-16 06:45:50 +00:00
3d82699605
Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
...
it doesn't currently use/maintain the chain properly. Also, make the
X86ISelLowering.cpp file 80-col clean.
llvm-svn: 28320
2006-05-16 06:45:34 +00:00
788db2c812
Replace "../whatever.td" with "whatever.td", so that out-of-tree backends
...
can just add lib/Target to TableGen includes.
llvm-svn: 28318
2006-05-16 06:39:36 +00:00
957cb6733a
Move function-live-in-handling code from the sdisel code to the scheduler.
...
This code should be emitted after legalize, so it can't be in sdisel.
Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG. The X86 backend is the only one currently using this hook.
llvm-svn: 28315
2006-05-16 06:10:58 +00:00
52d0c78de8
Print the vreg that livein physregs are live in
...
llvm-svn: 28314
2006-05-16 05:55:30 +00:00
5f0edfb849
Legalize FORMAL_ARGUMENTS nodes correctly, we don't want to legalize them once
...
for each argument.
llvm-svn: 28313
2006-05-16 05:49:56 +00:00
d2ca9abf57
Fit in 80 cols
...
llvm-svn: 28311
2006-05-16 04:20:24 +00:00
4abf33f56e
add an abort after every assert(0)
...
llvm-svn: 28310
2006-05-15 22:34:39 +00:00
26bb7c467f
For PR777:
...
Add an additional catch block to ensure that this function can't throw any
exceptions, even one's we're not expecting.
llvm-svn: 28309
2006-05-15 22:12:42 +00:00
fce45ffcd6
Improve comment, patch provided by Vladimir Prus!
...
llvm-svn: 28307
2006-05-15 18:35:02 +00:00
04a9e38369
Remove some dead code, identified by coverity.
...
llvm-svn: 28303
2006-05-15 05:48:32 +00:00
ffdc24b847
added a skeleton of the ARM backend
...
llvm-svn: 28301
2006-05-14 22:18:28 +00:00
63539389ca
LoadLibraryPermanently can theoretically throw an exception. Do not propagate
...
it out of 'ExecutionEngine::create'. This fixes a problem reported by coverity.
llvm-svn: 28293
2006-05-14 19:01:55 +00:00
78b8e977b2
Bug noticed, by inspection. Filename can be null.
...
llvm-svn: 28292
2006-05-14 19:00:53 +00:00
f64397ba1a
This function is not documented as throwing an exception and callers don't
...
handle it. Just silently fail.
llvm-svn: 28291
2006-05-14 18:53:09 +00:00
96749c4cec
inverted logic, caught by coverity
...
llvm-svn: 28290
2006-05-14 18:46:52 +00:00
35515557c7
remove some dead code identified by coverity
...
llvm-svn: 28289
2006-05-14 18:45:44 +00:00
47a6e63696
remove dead var
...
llvm-svn: 28287
2006-05-14 18:34:36 +00:00
3237da073e
remove dead variables
...
llvm-svn: 28286
2006-05-14 18:33:57 +00:00
18d0438148
Backing out last check-in for now. It's causing an infinite loop gccas lencode.
...
llvm-svn: 28284
2006-05-14 06:46:03 +00:00
215280d8b9
Update comment.
...
llvm-svn: 28283
2006-05-14 02:05:19 +00:00
99f2f79e2f
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
...
llvm-svn: 28279
2006-05-13 08:22:24 +00:00
d1915cfa6f
Revert an un-intended change
...
llvm-svn: 28278
2006-05-13 05:53:47 +00:00
3987a8532d
Add/Sub/Mul are safe to promote here as well. Incrementing a single-bit
...
bitfield now gives this code:
_plus:
lwz r2, 0(r3)
rlwimi r2, r2, 0, 1, 31
xoris r2, r2, 32768
stw r2, 0(r3)
blr
instead of this:
_plus:
lwz r2, 0(r3)
srwi r4, r2, 31
slwi r4, r4, 31
addis r4, r4, -32768
rlwimi r2, r4, 0, 0, 0
stw r2, 0(r3)
blr
this can obviously still be improved.
llvm-svn: 28275
2006-05-13 02:16:08 +00:00
69a0ce6261
Merge identical code.
...
llvm-svn: 28274
2006-05-13 02:11:14 +00:00
1ebbe6a22e
Implement simple promotion for cast elimination in instcombine. This is
...
currently very limited, but can be extended in the future. For example,
we now compile:
uint %test30(uint %c1) {
%c2 = cast uint %c1 to ubyte
%c3 = xor ubyte %c2, 1
%c4 = cast ubyte %c3 to uint
ret uint %c4
}
to:
_xor:
movzbl 4(%esp), %eax
xorl $1, %eax
ret
instead of:
_xor:
movb $1, %al
xorb 4(%esp), %al
movzbl %al, %eax
ret
More impressively, we now compile:
struct B { unsigned bit : 1; };
void xor(struct B *b) { b->bit = b->bit ^ 1; }
To (X86/PPC):
_xor:
movl 4(%esp), %eax
xorl $-2147483648, (%eax)
ret
_xor:
lwz r2, 0(r3)
xoris r2, r2, 32768
stw r2, 0(r3)
blr
instead of (X86/PPC):
_xor:
movl 4(%esp), %eax
movl (%eax), %ecx
movl %ecx, %edx
shrl $31, %edx
# TRUNCATE movb %dl, %dl
xorb $1, %dl
movzbl %dl, %edx
andl $2147483647, %ecx
shll $31, %edx
orl %ecx, %edx
movl %edx, (%eax)
ret
_xor:
lwz r2, 0(r3)
srwi r4, r2, 31
xori r4, r4, 1
rlwimi r2, r4, 31, 0, 0
stw r2, 0(r3)
blr
This implements InstCombine/cast.ll:test30.
llvm-svn: 28273
2006-05-13 02:06:03 +00:00
cd60d38b30
Remove some dead variables.
...
Fix a nasty bug in the memcmp optimizer where we used the wrong variable!
llvm-svn: 28269
2006-05-12 23:35:26 +00:00
94acc47654
Remove dead stuff
...
llvm-svn: 28268
2006-05-12 23:32:01 +00:00
768bc20b74
Fix build breakage :(
...
llvm-svn: 28267
2006-05-12 23:26:11 +00:00
b19ce6c810
More coverity fixes
...
llvm-svn: 28266
2006-05-12 21:14:20 +00:00
22f95b74ba
Dead variable
...
llvm-svn: 28265
2006-05-12 21:12:22 +00:00
ae48a894b1
Remove dead var, fix bad override.
...
llvm-svn: 28264
2006-05-12 21:09:57 +00:00
a726fc6dbf
If the register allocator cannot find a register to spill, try the aliases. If
...
that still fails (because all the register spill weights are inf), just grab
one.
llvm-svn: 28262
2006-05-12 19:07:46 +00:00
db30388d48
Remove dead code
...
llvm-svn: 28261
2006-05-12 19:03:56 +00:00
227d442d01
Fix accidentally committed patch.
...
llvm-svn: 28260
2006-05-12 18:20:39 +00:00
d63ec521c5
Actually override the right method. :)
...
Bug identified by coverity.
llvm-svn: 28259
2006-05-12 18:19:25 +00:00
132322b96e
remove dead variable.
...
llvm-svn: 28258
2006-05-12 18:17:25 +00:00
1971e8a77b
Fix iterator invalidation bug, identified by Coverity.
...
llvm-svn: 28257
2006-05-12 18:13:11 +00:00
1fe2d2c600
Fix a hypothetical memory leak, identified by Coverity. In practice, this
...
object is never deleted though.
llvm-svn: 28256
2006-05-12 18:10:12 +00:00
53cdb2f2b0
Remove dead vars
...
llvm-svn: 28255
2006-05-12 18:06:45 +00:00
da076e41ab
remove dead vars
...
llvm-svn: 28254
2006-05-12 18:04:28 +00:00
fe211deedf
Remove dead variable
...
llvm-svn: 28253
2006-05-12 18:02:04 +00:00
afe72481f6
Comment out dead variables
...
llvm-svn: 28252
2006-05-12 17:57:54 +00:00
69fb378858
When reading the symbol table, make sure to delete the ArchiveMember
...
created by reading the symbol table.
llvm-svn: 28251
2006-05-12 17:56:20 +00:00
936cd3390d
Remove dead var
...
llvm-svn: 28250
2006-05-12 17:50:35 +00:00
ce9ac0cdab
Remove dead variable
...
llvm-svn: 28249
2006-05-12 17:41:45 +00:00
f76c42776d
remove dead variable.
...
llvm-svn: 28248
2006-05-12 17:33:59 +00:00
9cd2ef34e6
Remove dead variable.
...
llvm-svn: 28247
2006-05-12 17:31:21 +00:00
8c02c3f41a
Compile:
...
%tmp152 = setgt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%tmp159 = setlt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%bothcond2 = or bool %tmp152, %tmp159 ; <bool> [#uses=1]
To setne, not setune, which causes an assertion fault.
llvm-svn: 28244
2006-05-12 17:03:46 +00:00
a296339c87
Fix PowerPC/2006-05-12-rlwimi-crash.ll
...
Nate, please verify that if InsertMask is 0, rlwimi shouldn't be used.
This fixes the crash and causes no PPC testsuite regressions.
llvm-svn: 28243
2006-05-12 16:29:37 +00:00
5fea9f0a93
Add a method to generate a string representation from a TargetData.
...
This continues the work on PR 761.
llvm-svn: 28239
2006-05-12 07:01:44 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
...
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
d7c77b8c56
Fix some tabbing issues.
...
llvm-svn: 28237
2006-05-12 06:06:55 +00:00
6a6886185b
Backing out fix for PR770. Need to re-apply it after live range splitting is possible
...
llvm-svn: 28236
2006-05-12 06:06:34 +00:00
095c9d9b7f
Duh. That could take a long time.
...
llvm-svn: 28235
2006-05-12 06:05:18 +00:00
8d7774cb1d
Add a new constructor to TargetData that builds a TargetData from its
...
string representation.
This is part of PR 761.
llvm-svn: 28234
2006-05-12 05:49:47 +00:00
66adee93aa
Two simplifications for token factor nodes: simplify tf(x,x) -> x.
...
simplify tf(x,y,y,z) -> tf(x,y,z).
llvm-svn: 28233
2006-05-12 05:01:37 +00:00
afed73eebe
Add capability to scheduler to commute nodes for profit.
...
If a two-address code whose first operand has uses below, it should be commuted
when possible.
llvm-svn: 28230
2006-05-12 01:58:24 +00:00
c30a5558f2
Typo! How did we commute nodes before?!
...
llvm-svn: 28229
2006-05-12 01:46:26 +00:00
22acb80971
For extra sanity checking, fill free'd memory with garbage so we know that
...
people aren't reusing machine code buffers at all.
llvm-svn: 28228
2006-05-12 00:03:12 +00:00
3c729b9e5d
Fix some bugs in the freelist manipulation code.
...
Finally, implement ExecutionEngine::freeMachineCodeForFunction.
llvm-svn: 28227
2006-05-11 23:56:57 +00:00
d38c22bdd3
Refactor scheduler code. Move register-reduction list scheduler to a
...
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
llvm-svn: 28226
2006-05-11 23:55:42 +00:00
873ef133ce
Significantly revamp allocation of machine code to use free lists, real
...
allocation policies and much more. All this complexity, and we have no
functionality change, woo! :)
llvm-svn: 28225
2006-05-11 23:08:08 +00:00
1443bc52be
Refactor some code, making it simpler.
...
When doing the initial pass of constant folding, if we get a constantexpr,
simplify the constant expr like we would do if the constant is folded in the
normal loop.
This fixes the missed-optimization regression in
Transforms/InstCombine/getelementptr.ll last night.
llvm-svn: 28224
2006-05-11 17:11:52 +00:00
dd7230c9e0
Add MOV16_rm / MOV32_rm and MOV16_mr / MOV32_mr to isLoadFromStackSlot and isStoreToStackSlot
...
llvm-svn: 28223
2006-05-11 07:33:49 +00:00
47926aff96
Set weight of zero length intervals to infinite to prevent them from being
...
spilled.
llvm-svn: 28220
2006-05-11 07:29:24 +00:00
db6aa4896b
Backing out previous check-in.
...
llvm-svn: 28219
2006-05-11 07:28:16 +00:00
6ad040a6bc
If the live interval legnth is essentially zero, i.e. in every live range
...
the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.
llvm-svn: 28217
2006-05-10 22:30:41 +00:00
a36ee4ea34
Two changes:
...
1. Implement InstCombine/deadcode.ll by not adding instructions in unreachable
blocks (due to constants in conditional branches/switches) to the worklist.
This causes them to be deleted before instcombine starts up, leading to
better optimization.
2. In the prepass over instructions, do trivial constprop/dce as we go. This
has the effect of improving the effectiveness of #1 . In addition, it
*significantly* speeds up instcombine on test cases with large amounts of
constant folding code (for example, that produced by code specialization
or partial evaluation). In one example, it speeds up instcombine from
0.0589s to 0.0224s with a release build (a 2.6x speedup).
llvm-svn: 28215
2006-05-10 19:00:36 +00:00
b25cb79604
Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is
...
really a bad codegen bug that LLC happens to get lucky with. I must chat with
Nate for the proper fix.
llvm-svn: 28213
2006-05-10 06:38:32 +00:00
9665ba053f
Templatify RegReductionPriorityQueue
...
llvm-svn: 28212
2006-05-10 06:16:44 +00:00
bb7ff6690f
Add an assertion for a common error
...
llvm-svn: 28210
2006-05-10 04:32:43 +00:00
1a225d23ae
Fix PR773
...
llvm-svn: 28207
2006-05-09 18:20:51 +00:00
f801792e08
Fix a regression in my patch from last night that broke the llvmgcc4 build on
...
ppc
llvm-svn: 28205
2006-05-09 16:41:59 +00:00
2814134a5d
Indent .data/.text in the .s file
...
llvm-svn: 28204
2006-05-09 16:15:00 +00:00
7d693898ee
Add pseudo dependency to force a def&use operand to be scheduled last (unless
...
the distance between the def and another use is much longer). This is under
option control for now "-sched-lower-defnuse".
llvm-svn: 28201
2006-05-09 07:13:34 +00:00
2c74848af1
Debugging info
...
llvm-svn: 28200
2006-05-09 06:55:15 +00:00
fc532fe1b7
Remove a completed entry.
...
llvm-svn: 28199
2006-05-09 06:54:05 +00:00
ae45020720
PR 770 - permit coallescing of registers in subset register classes.
...
llvm-svn: 28197
2006-05-09 06:37:48 +00:00
4ebc6a2311
Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code.
...
llvm-svn: 28194
2006-05-09 05:33:48 +00:00
8c2bfc0659
Oh yeah, there are two of these now, unify both.
...
llvm-svn: 28192
2006-05-09 05:24:50 +00:00
6341df8069
Setting SwitchToSectionDirective properly in the MASM backend permits a bunch
...
of code to be unified.
llvm-svn: 28191
2006-05-09 05:23:12 +00:00
0b7acaf027
MASM doesn't have one of these.
...
llvm-svn: 28190
2006-05-09 05:21:47 +00:00
d36cc2b610
Don't prefix section directives with a tab. Doing so causes blank lines to
...
be emitted to the .s file.
llvm-svn: 28189
2006-05-09 05:19:59 +00:00
e64f764d25
Make the masm codepath work like the normal code path.
...
llvm-svn: 28188
2006-05-09 05:15:58 +00:00
e0006c6794
Preserve prior behavior
...
llvm-svn: 28187
2006-05-09 05:15:24 +00:00
c0f0dfa56f
The MASM asmprinter has been fixed, these hacks are no longer needed.
...
llvm-svn: 28186
2006-05-09 05:13:34 +00:00
d0201946ad
Fix the MASM asmprinter's lies. It does not want to emit code to .text/.data
...
it wants it emitted to _text/_data.
llvm-svn: 28185
2006-05-09 05:12:53 +00:00
8488ba2e41
Split SwitchSection into SwitchTo{Text|Data}Section methods.
...
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
8587f8885d
Some notes and thoughts to myself
...
llvm-svn: 28182
2006-05-09 04:58:46 +00:00
4fe87d67c4
Patch to make some xforms preserve each other. Patch contributed by
...
Domagoj Babic!
llvm-svn: 28181
2006-05-09 04:13:41 +00:00
6d8dd189f6
Move some methods out of line so that MutexGuard.h isn't needed in a public header.
...
llvm-svn: 28179
2006-05-08 22:00:52 +00:00
aa193d80a9
Another bad case I noticed
...
llvm-svn: 28177
2006-05-08 21:39:45 +00:00
5bcea612f4
add a note
...
llvm-svn: 28176
2006-05-08 21:24:21 +00:00
446e1ef26a
Make the case I just checked in stronger. Now we compile this:
...
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
to:
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test2:
add r2, r3, r4
extsh r2, r2
srwi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28175
2006-05-08 21:18:59 +00:00
29062da0ac
Implement and_sext.ll:test3, generating:
...
_test4:
srawi r3, r3, 16
blr
instead of:
_test4:
srwi r2, r3, 16
extsh r3, r2
blr
for:
short test4(unsigned X) {
return (X >> 16);
}
llvm-svn: 28174
2006-05-08 20:59:41 +00:00
ce6646c366
Yet more readme updating
...
llvm-svn: 28172
2006-05-08 20:54:02 +00:00
2935d8190c
Compile this:
...
short test4(unsigned X) {
return (X >> 16);
}
to:
_test4:
movl 4(%esp), %eax
sarl $16, %eax
ret
instead of:
_test4:
movl $-65536, %eax
andl 4(%esp), %eax
sarl $16, %eax
ret
llvm-svn: 28171
2006-05-08 20:51:54 +00:00
68a45419cc
New note about something bad happening in target independent optimizers
...
llvm-svn: 28170
2006-05-08 20:08:28 +00:00
0eb8f2e496
Proving once again that I am not as smart as the compiler
...
llvm-svn: 28169
2006-05-08 19:09:24 +00:00
9b6d4c2968
Fold more shifts into inserts, and update the README
...
llvm-svn: 28168
2006-05-08 17:38:32 +00:00
78da6792e7
Fold shifts with undef operands.
...
llvm-svn: 28167
2006-05-08 17:29:49 +00:00
10c653744e
When tracking demanded bits, if any bits from the sext of an SRA are demanded,
...
then so is the input sign bit. This fixes mediabench/g721 on X86.
llvm-svn: 28166
2006-05-08 17:22:53 +00:00
d7a19102d1
Make emission of jump tables a bit less conservative; they are now required
...
to be only 31.25% dense, rather than 75% dense.
llvm-svn: 28165
2006-05-08 16:51:36 +00:00
9733bde74c
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
...
movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
llvm-svn: 28164
2006-05-08 08:01:26 +00:00
dc996b3f6c
Update some stuff now that the new rlwimi code has gone in
...
llvm-svn: 28162
2006-05-08 02:52:38 +00:00
e5ce5bb6da
Fix PR772
...
llvm-svn: 28161
2006-05-08 01:35:01 +00:00
6732dcd5b3
Typo's
...
llvm-svn: 28158
2006-05-07 10:10:20 +00:00
04196acdcb
Unlike Unix, Windows won't let a file be implicitly replaced via renaming without explicit permission.
...
llvm-svn: 28157
2006-05-07 02:51:51 +00:00
1333cead5b
New rlwimi implementation, which is superior to the old one. There are
...
still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same bitfield. More regression tests
to come.
llvm-svn: 28156
2006-05-07 00:23:38 +00:00
cd4a643728
Use ComputeMaskedBits to determine # sign bits as a fallback. This allows us
...
to handle all kinds of stuff, including silly things like:
sextinreg(setcc,i16) -> setcc.
llvm-svn: 28155
2006-05-06 23:48:13 +00:00
4f3de3e33c
Add some more sign propagation cases
...
llvm-svn: 28154
2006-05-06 23:40:29 +00:00
9978476c14
Apply bug fix supplied by Greg Pettyjohn for a bug he found: '<invalid>' is not a legal path on Windows.
...
llvm-svn: 28153
2006-05-06 23:25:53 +00:00
7e7bcf3a54
Simplify some code, add a couple minor missed folds
...
llvm-svn: 28152
2006-05-06 23:06:26 +00:00
751817c54f
constant fold sign_extend_inreg
...
llvm-svn: 28151
2006-05-06 23:05:41 +00:00
2a4d7b845b
remove cases handled elsewhere
...
llvm-svn: 28150
2006-05-06 22:43:44 +00:00
f86075731d
Add some more simple sign bit propagation cases.
...
llvm-svn: 28149
2006-05-06 22:39:59 +00:00
ce9b9fe6eb
Fix some loose ends in MASM support.
...
llvm-svn: 28148
2006-05-06 21:27:14 +00:00
1ecb2a2dac
Use the new TargetLowering::ComputeNumSignBits method to eliminate
...
sign_extend_inreg operations. Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:
short test(short X, short x) {
int Y = X+x;
return (Y >> 1);
}
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
into:
_test:
add r2, r3, r4
srawi r3, r2, 1
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test:
add r2, r3, r4
srawi r2, r2, 1
extsh r3, r2
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28146
2006-05-06 09:30:03 +00:00
7206d74f0c
Add some really really simple code for computing sign-bit propagation.
...
This will certainly be enhanced in the future.
llvm-svn: 28145
2006-05-06 09:27:13 +00:00
21cd99024a
When inserting casts, be careful of where we put them. We cannot insert
...
a cast immediately before a PHI node.
This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
llvm-svn: 28143
2006-05-06 09:10:37 +00:00
1d441adfbf
Move some code around.
...
Make the "fold (and (cast A), (cast B)) -> (cast (and A, B))" transformation
only apply when both casts really will cause code to be generated. If one or
both doesn't, then this xform doesn't remove a cast.
This fixes Transforms/InstCombine/2006-05-06-Infloop.ll
llvm-svn: 28141
2006-05-06 09:00:16 +00:00
6d4a2dc4ad
Teach the X86 backend about non-i32 inline asm register classes.
...
llvm-svn: 28139
2006-05-06 00:29:37 +00:00
86a1467fc0
Fold (trunc (srl x, c)) -> (srl (trunc x), c)
...
llvm-svn: 28138
2006-05-06 00:11:52 +00:00
907e392dba
Fold trunc(any_ext). This gives stuff like:
...
27,28c27
< movzwl %di, %edi
< movl %edi, %ebx
---
> movw %di, %bx
llvm-svn: 28137
2006-05-05 22:56:26 +00:00
57f8c5a387
Shrink shifts when possible.
...
llvm-svn: 28136
2006-05-05 22:53:17 +00:00
0f64932a5c
Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE
...
llvm-svn: 28135
2006-05-05 22:32:12 +00:00
8b9e11c110
Print a grouping around inline asm blocks so that we can tell when we are
...
using them.
llvm-svn: 28134
2006-05-05 21:50:04 +00:00
c22d4bede5
Print *some* grouping around inline asm blocks so we know where they are.
...
llvm-svn: 28133
2006-05-05 21:48:50 +00:00
a633c31319
Indent multiline asm strings more nicely
...
llvm-svn: 28132
2006-05-05 21:47:05 +00:00
44a73e9fa5
Teach the code generator to use cvtss2sd as extload f32 -> f64
...
llvm-svn: 28131
2006-05-05 21:35:18 +00:00
3d26577396
Fold (fpext (load x)) -> (extload x)
...
llvm-svn: 28130
2006-05-05 21:34:35 +00:00
3e3f2c63c3
More aggressively sink GEP offsets into loops. For example, before we
...
generated:
movl 8(%esp), %eax
movl %eax, %edx
addl $4316, %edx
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, (%edx)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
movl %edx, 4460(%eax)
ret
...
Now we generate:
movl 8(%esp), %eax
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, 4316(%eax)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
movl %ecx, 4460(%eax)
ret
... which uses one fewer register.
llvm-svn: 28129
2006-05-05 21:17:49 +00:00
e745c7de0e
Fix an infinite loop compiling oggenc last night.
...
llvm-svn: 28128
2006-05-05 20:51:30 +00:00
52c22512b9
Need extload patterns after Chris' DAG combiner changes
...
llvm-svn: 28127
2006-05-05 08:23:07 +00:00
3af1053488
Implement InstCombine/cast.ll:test29
...
llvm-svn: 28126
2006-05-05 06:39:07 +00:00
25a5283a86
Fold some common code.
...
llvm-svn: 28124
2006-05-05 06:32:04 +00:00
002ee91457
Implement:
...
// fold (and (sext x), (sext y)) -> (sext (and x, y))
// fold (or (sext x), (sext y)) -> (sext (or x, y))
// fold (xor (sext x), (sext y)) -> (sext (xor x, y))
// fold (and (aext x), (aext y)) -> (aext (and x, y))
// fold (or (aext x), (aext y)) -> (aext (or x, y))
// fold (xor (aext x), (aext y)) -> (aext (xor x, y))
llvm-svn: 28123
2006-05-05 06:31:05 +00:00
5ac4293606
Pull and through and/or/xor. This compiles some bitfield code to:
...
mov EAX, DWORD PTR [ESP + 4]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
or EDX, ECX
and EDX, -2147483648
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
ret
instead of:
sub ESP, 4
mov DWORD PTR [ESP], ESI
mov EAX, DWORD PTR [ESP + 8]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
mov ESI, ECX
and ESI, -2147483648
and EDX, -2147483648
or EDX, ESI
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
mov ESI, DWORD PTR [ESP]
add ESP, 4
ret
llvm-svn: 28122
2006-05-05 06:10:43 +00:00
812646aa0c
Implement a variety of simplifications for ANY_EXTEND.
...
llvm-svn: 28121
2006-05-05 05:58:59 +00:00
8d6fc20181
Factor some code, add these transformations:
...
// fold (and (trunc x), (trunc y)) -> (trunc (and x, y))
// fold (or (trunc x), (trunc y)) -> (trunc (or x, y))
// fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y))
llvm-svn: 28120
2006-05-05 05:51:50 +00:00
ddb6cc1d8e
Better implementation of truncate. ISel matches it to a pseudo instruction
...
that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.
llvm-svn: 28119
2006-05-05 05:40:20 +00:00
304bbf3b1d
New note, Nate, please check to see if I'm full of it :)
...
llvm-svn: 28118
2006-05-05 05:36:15 +00:00
78a7f0e05e
Fix VC++ compilation error.
...
llvm-svn: 28117
2006-05-05 01:47:05 +00:00
7a3ecf7993
Sink noop copies into the basic block that uses them. This reduces the number
...
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.
This reduces the load on the coallescer and register allocator. For example
on a codec on X86, we went from:
1643 asm-printer - Number of machine instrs printed
419 liveintervals - Number of loads/stores folded into instructions
1144 liveintervals - Number of identity moves eliminated after coalescing
1022 liveintervals - Number of interval joins performed
282 liveintervals - Number of intervals after coalescing
1304 liveintervals - Number of original intervals
86 regalloc - Number of times we had to backtrack
1.90232 regalloc - Ratio of intervals processed over total intervals
40 spiller - Number of values reused
182 spiller - Number of loads added
121 spiller - Number of stores added
132 spiller - Number of register spills
6 twoaddressinstruction - Number of instructions commuted to coalesce
360 twoaddressinstruction - Number of two-address instructions
to:
1636 asm-printer - Number of machine instrs printed
403 liveintervals - Number of loads/stores folded into instructions
1155 liveintervals - Number of identity moves eliminated after coalescing
1033 liveintervals - Number of interval joins performed
279 liveintervals - Number of intervals after coalescing
1312 liveintervals - Number of original intervals
76 regalloc - Number of times we had to backtrack
1.88998 regalloc - Ratio of intervals processed over total intervals
1 spiller - Number of copies elided
41 spiller - Number of values reused
191 spiller - Number of loads added
114 spiller - Number of stores added
128 spiller - Number of register spills
4 twoaddressinstruction - Number of instructions commuted to coalesce
356 twoaddressinstruction - Number of two-address instructions
On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted. It increases the number
of register coallesces.
llvm-svn: 28115
2006-05-05 01:04:50 +00:00
b6277c510c
Adjust to use proper TargetData copy ctor
...
llvm-svn: 28112
2006-05-04 21:18:40 +00:00
abdf4d569c
Final pass of minor cleanups for MachineInstr
...
llvm-svn: 28110
2006-05-04 19:36:09 +00:00
9add880566
Initial support for register pressure aware scheduling. The register reduction
...
scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.
llvm-svn: 28108
2006-05-04 19:16:39 +00:00
53af9da363
Remove redundancy and a level of indirection when creating machine operands
...
llvm-svn: 28107
2006-05-04 19:14:44 +00:00
469647bf38
Remove and simplify some more machineinstr/machineoperand stuff.
...
llvm-svn: 28105
2006-05-04 18:16:01 +00:00
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
...
llvm-svn: 28104
2006-05-04 18:05:43 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
...
llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fb29692055
Fix Transforms/InstCombine/2006-05-04-DemandedBitCrash.ll
...
llvm-svn: 28101
2006-05-04 17:33:35 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
...
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
15c52bda1d
Change "value" in MachineOperand to be a GlobalValue, as that is the only
...
thing that can be in it. Remove a dead method.
llvm-svn: 28098
2006-05-04 17:02:51 +00:00
13d5f3eb05
Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones).
...
Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of
CRRC seems to cause failures as well. Further investigation is required.
llvm-svn: 28097
2006-05-04 16:56:45 +00:00
06041abeb6
Make external globals public; other minor cleanup.
...
llvm-svn: 28096
2006-05-04 16:20:22 +00:00
f812a4fa75
Make Intel syntax the default when LLVM is built with VC++.
...
llvm-svn: 28095
2006-05-04 16:19:27 +00:00
ee64b6b40f
Remove a bunch more dead V9 specific stuff
...
llvm-svn: 28094
2006-05-04 01:26:39 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
...
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
6e663f1c1e
Remove some more V9-specific stuff.
...
llvm-svn: 28092
2006-05-04 00:49:59 +00:00
9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
...
llvm-svn: 28091
2006-05-04 00:44:25 +00:00
2aef59f123
Simplify handling of relocations
...
llvm-svn: 28090
2006-05-04 00:42:08 +00:00
8b1cde2bbe
Use movsd to shuffle in the lowest two elements of a v4f32 / v4i32 vector when
...
movlps cannot be used (e.g. when load from m64 has multiple uses).
llvm-svn: 28089
2006-05-03 20:32:03 +00:00
e3a9c70ba0
Change from using MachineRelocation ctors to using static methods
...
in MachineRelocation to create Relocations.
llvm-svn: 28088
2006-05-03 20:30:20 +00:00
005d7174c8
minor cleanups, no functionality change
...
llvm-svn: 28087
2006-05-03 18:55:56 +00:00
9e68942d78
inline a simple method
...
llvm-svn: 28083
2006-05-03 17:21:32 +00:00
1d8ee1fc80
Suck block address tracking out of targets into the JIT Emitter. This
...
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.
llvm-svn: 28082
2006-05-03 17:10:41 +00:00
9954bc9c19
Fix a bug in Owen's checkin that broke the CBE on all non sparc v9 platforms.
...
llvm-svn: 28081
2006-05-03 05:48:41 +00:00
43b1ed7e3d
Teach the x86 jit how to handle jump tables not directly used by a jump
...
instruction.
llvm-svn: 28080
2006-05-03 04:52:47 +00:00
df4883971e
Finish up the initial jump table implementation by allowing jump tables to
...
not be 100% dense. Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.
llvm-svn: 28079
2006-05-03 03:48:02 +00:00
ffef8b9412
Bottom up register pressure reduction work: clean up some hacks and enhanced
...
the heuristic to further reduce spills for several test cases. (Note, it may
not necessarily translate to runtime win!)
llvm-svn: 28076
2006-05-03 02:10:45 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
37c39b9c62
Align function bodies correctly.
...
llvm-svn: 28073
2006-05-03 01:03:20 +00:00
77fe5b4459
Simplify some code. Don't add memory blocks to the Blocks list twice.
...
llvm-svn: 28071
2006-05-03 00:54:49 +00:00
667a056e11
Add assertions that verify that the actual arguments to a call or invoke match
...
the prototype of the called function.
llvm-svn: 28070
2006-05-03 00:48:22 +00:00
d8b192ba3b
Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
...
llvm-svn: 28069
2006-05-03 00:32:55 +00:00
0267807ddc
Keep the alpha JIT similar to the PPC/X86 jits
...
llvm-svn: 28068
2006-05-03 00:31:21 +00:00
0574e47dca
Simplify some code
...
llvm-svn: 28066
2006-05-03 00:13:06 +00:00
b8065a9a3a
Several related changes:
...
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
from the MachineCodeEmitter interface, and reducing the amount of target-
specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
*right* next to the functions that they belong to, instead of in a separate
pool of memory. This makes all memory for a function be contiguous, and
means the JITEmitter only tracks one block of memory now.
llvm-svn: 28065
2006-05-02 23:22:24 +00:00
233391f5f5
Remove some stuff from the README
...
llvm-svn: 28063
2006-05-02 22:43:31 +00:00
23621fe8f4
Do not make the JIT memory manager manage the memory for globals. Instead
...
just have the JIT malloc them.
llvm-svn: 28062
2006-05-02 21:57:51 +00:00
25b95ed868
Minor cleanups, no functionality change.
...
llvm-svn: 28061
2006-05-02 21:44:14 +00:00
e1c96369e2
Fix a purely hypothetical problem (for now): emitWord emits in the host
...
byte format. This doesn't work when using the code emitter in a cross target
environment. Since the code emitter is only really used by the JIT, this
isn't a current problem, but if we ever start emitting .o files, it would be.
llvm-svn: 28060
2006-05-02 19:14:47 +00:00
c9aa3715e8
Refactor the machine code emitter interface to pull the pointers for the current
...
code emission location into the base class, instead of being in the derived classes.
This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments. This implements feature request #1 of PR469.
llvm-svn: 28059
2006-05-02 18:27:26 +00:00
bbcbf48aab
Since we don't handle callee-save CRs right yet, don't allocate them. Also
...
don't step on R11 in the middle of a function when saving and restoring CRs
llvm-svn: 28058
2006-05-02 17:37:31 +00:00
4971ba5f41
Print function number instead of name
...
llvm-svn: 28057
2006-05-02 17:36:46 +00:00
287dc5be0d
Hooray, everyone now uses the same printBasicBlockLabel implementation
...
llvm-svn: 28056
2006-05-02 17:34:51 +00:00
67a3aa2aaa
Remove dead method
...
llvm-svn: 28055
2006-05-02 17:20:28 +00:00
5bc9c583e3
There is no reason to use a virtual method to store this word.
...
llvm-svn: 28053
2006-05-02 17:16:20 +00:00
bb1c345ec6
Remove the debug machine code emitter. The "FilePrinterEmitter" is more
...
useful for debugging.
llvm-svn: 28051
2006-05-02 16:59:24 +00:00
b9d4f8324d
Extend printBasicBlockLabel a bit so that it can be used to print all
...
basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
01364fbba8
Update the PPC compilation callback code to not need weird abi-violating
...
prologs and epilogs, keep all the asm in one place, and remove use of
compiler builtin functions.
llvm-svn: 28049
2006-05-02 04:50:05 +00:00
2d3a02725d
Add pass ID's for various passes, so they can be AddRequiredID. Patch by
...
Domagoj Babic!
llvm-svn: 28048
2006-05-02 04:24:36 +00:00
470f431f44
De-virtualize SwitchSection.
...
llvm-svn: 28047
2006-05-02 03:58:45 +00:00
f34ddb1e0d
De-virtualize EmitZeroes.
...
llvm-svn: 28046
2006-05-02 03:46:13 +00:00
bfe9ffb449
Finish support for Microsoft ML/MASM. May still be a few rough edges.
...
llvm-svn: 28045
2006-05-02 03:11:50 +00:00
24a62a9bc1
Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work).
...
llvm-svn: 28044
2006-05-02 01:16:28 +00:00
fd0a5478a1
Fix a latent bug that my spiller patch last week exposed: we were leaving
...
instructions in the virtregfolded map that were deleted. Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map. The solution is to remove entries
from the map when we delete the instructions.
llvm-svn: 28041
2006-05-01 22:03:24 +00:00
ab7dbe0cc9
When promoting a load to a reg-reg copy, where the load was a previous
...
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.
llvm-svn: 28040
2006-05-01 21:17:10 +00:00
4dee67c2cd
Remove previous patch, which wasn't quite right.
...
llvm-svn: 28039
2006-05-01 21:16:03 +00:00
85e9909755
Put PHI/INLINEASM into the correct namespace.
...
llvm-svn: 28037
2006-05-01 17:00:49 +00:00
0d084fb9ca
Dis-favor stores more
...
llvm-svn: 28035
2006-05-01 09:20:44 +00:00
24e795496d
Bottom up register-pressure reduction scheduler now pushes store operations
...
up the schedule. This helps code that looks like this:
loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...
Without this change, the stores and computations are more likely to
interleave:
loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...
This can increase the number of spills if we are unlucky.
llvm-svn: 28033
2006-05-01 09:14:40 +00:00
10ff7b27ce
Didn't mean ScheduleDAGList.cpp to make the last checkin.
...
llvm-svn: 28030
2006-05-01 08:56:34 +00:00
a656242690
Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions.
...
llvm-svn: 28029
2006-05-01 08:54:57 +00:00
563f0417d2
Remove %'s from register names when in intel mode.
...
llvm-svn: 28027
2006-05-01 05:53:50 +00:00
25f55ae74a
Format #APP lines a bit nicer
...
llvm-svn: 28026
2006-05-01 04:11:03 +00:00
f71f0f2e0b
Local spiller kills a store if the folded restore is turned into a copy.
...
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.
llvm-svn: 28024
2006-04-30 08:41:47 +00:00
71c2e0f262
Mingw32 patches supplied by Anton Korobeynikov.
...
llvm-svn: 28023
2006-04-29 18:41:44 +00:00
2b48a94413
Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
...
with some changes I have to the new CFE.
llvm-svn: 28022
2006-04-28 23:33:20 +00:00
d369603df9
I can't spell: Register, not Regsiter.
...
llvm-svn: 28021
2006-04-28 23:19:39 +00:00
b244b80172
Implemented x86 inline asm b, h, w, k modifiers.
...
llvm-svn: 28020
2006-04-28 23:11:40 +00:00
655d08fda8
Fix InstCombine/2006-04-28-ShiftShiftLongLong.ll
...
llvm-svn: 28019
2006-04-28 22:21:41 +00:00
84b49d51be
Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
...
llvm-svn: 28017
2006-04-28 21:56:10 +00:00
88decded82
Initial caller side support (for CCC only, not FastCC) of 128-bit vector
...
passing by value.
llvm-svn: 28015
2006-04-28 21:29:37 +00:00
68a44dc445
Bare-bone X86 inline asm printer support.
...
llvm-svn: 28014
2006-04-28 21:19:05 +00:00
c5e8ce8b8c
Remove the temporary option: -no-isel-fold-inflight
...
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
3cd4362ade
Implement four-wide shuffle with 2 shufps if no more than two elements come
...
from each vector. e.g.
shuffle(G1, G2, 7, 1, 5, 2)
==>
movaps _G2, %xmm0
shufps $151, _G1, %xmm0
shufps $216, %xmm0, %xmm0
llvm-svn: 28011
2006-04-28 07:03:38 +00:00
1b7a51520c
Fix PR743: emit -help output of a tool to cout, not cerr.
...
llvm-svn: 28010
2006-04-28 05:36:25 +00:00
d43c5c6046
TargetLowering::LowerArguments should return a VBIT_CONVERT of
...
FORMAL_ARGUMENTS SDOperand in the return result vector.
llvm-svn: 28009
2006-04-28 05:25:15 +00:00
79c50d96c9
Mapping of physregs can make it so that the designated and input physregs are
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the same. In this case, don't emit a noop copy.
llvm-svn: 28008
2006-04-28 04:43:18 +00:00
e63d808b6e
Fix Transforms/Reassociate/2006-04-27-ReassociateVector.ll
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llvm-svn: 28007
2006-04-28 04:14:49 +00:00
f0157cb0bc
Use movaps instead of movapd for spill / restore.
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llvm-svn: 28005
2006-04-28 02:23:35 +00:00
51ab4498e7
Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
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node can be folded.
llvm-svn: 28003
2006-04-28 02:09:19 +00:00
84e95d00b5
When we have a two-address instruction where the input cannot be clobbered
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and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 01:46:50 +00:00
a4c2c4a276
Add a note
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llvm-svn: 27999
2006-04-28 00:04:05 +00:00
b209131b56
Add a note
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llvm-svn: 27998
2006-04-27 21:40:57 +00:00
b6cb64b7e6
Add support for inserting undef into a vector. This implements
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Transforms/InstCombine/vec_insert_to_shuffle.ll
llvm-svn: 27997
2006-04-27 21:14:21 +00:00
f4f3f0d25f
Make x86 isel lowering produce tailcall nodes. They are match to normal calls
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for now.
Patch contributed by Alexander Friedman.
llvm-svn: 27994
2006-04-27 08:40:39 +00:00
ec04a37edd
A couple of new entries.
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llvm-svn: 27993
2006-04-27 08:31:33 +00:00
89001ad729
Support for passing 128-bit vector arguments via XMM registers.
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llvm-svn: 27992
2006-04-27 08:31:10 +00:00
3784f3c57c
Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses
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(VAND, VADD, etc.). Legalizer will assert otherwise.
llvm-svn: 27991
2006-04-27 08:29:42 +00:00
a0374e1bed
Oops
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llvm-svn: 27989
2006-04-27 05:44:50 +00:00
24eb3f4765
Bug fix: not updating NumIntRegs.
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llvm-svn: 27988
2006-04-27 05:35:28 +00:00
393d96a56c
Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll and
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PR748.
llvm-svn: 27987
2006-04-27 05:01:07 +00:00
48940d16b2
- Clean up formal argument lowering code. Prepare for vector pass by value work.
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- Fixed vararg support.
llvm-svn: 27985
2006-04-27 01:32:22 +00:00
f98b4aa2e7
Fix some nondeterminstic behavior in the mem2reg pass that (in addition to
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nondeterminism being bad) could cause some trivial missed optimizations (dead
phi nodes being left around for later passes to clean up).
With this, llvm-gcc4 now bootstraps and correctly compares. I don't know
why I never tried to do it before... :)
llvm-svn: 27984
2006-04-27 01:14:43 +00:00
e8cbdbf314
Implement Transforms/IndVarsSimplify/complex-scev.ll, a case where we didn't
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recognize some simple affine IV's.
llvm-svn: 27982
2006-04-26 18:34:07 +00:00
1c39903297
Fix fastcc failures.
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llvm-svn: 27980
2006-04-26 18:21:31 +00:00
e0bcfbe811
Switching over FORMAL_ARGUMENTS mechanism to lower call arguments.
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llvm-svn: 27975
2006-04-26 01:20:17 +00:00
9618df1190
Don't forget return void.
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llvm-svn: 27974
2006-04-25 23:03:35 +00:00
4530327c04
Keep the stack from on darwin 16-byte aligned. This fixes many JIT
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failres.
llvm-svn: 27973
2006-04-25 20:54:26 +00:00
a9467aab0a
Separate LowerOperation() into multiple functions, one per opcode.
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llvm-svn: 27972
2006-04-25 20:13:52 +00:00
3c775bcd86
slightly more useful error message
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llvm-svn: 27971
2006-04-25 19:33:41 +00:00
f5a713d273
better c99 struct handling
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llvm-svn: 27970
2006-04-25 19:33:23 +00:00
4cc3e0b05f
Fix a typo.
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llvm-svn: 27968
2006-04-25 17:48:41 +00:00
48ccd3f826
Fix a warning
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llvm-svn: 27967
2006-04-25 17:46:32 +00:00
318bb96f9e
No functionality changes, but cleaner code with correct comments.
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llvm-svn: 27966
2006-04-25 04:45:59 +00:00
Evan Cheng