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220 Commits

Author SHA1 Message Date
Jim Grosbach 0c51bb4b25 Parameterize ARMPseudoInst size property. 
llvm-svn: 120353
 2010-11-29 23:48:41 +00:00
Jim Grosbach 58bc36a3a9 ARM Pseudo-ize tBR_JTr. 
llvm-svn: 120310
 2010-11-29 19:32:47 +00:00
Jim Grosbach 150b1ad7f8 Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos. 
llvm-svn: 120303
 2010-11-29 18:37:44 +00:00
Jim Grosbach 5876e41c9f trailing whitespace 
llvm-svn: 119863
 2010-11-19 22:42:55 +00:00
Jim Grosbach 09d7bfd886 Add ARM encoding information for STRD. 
llvm-svn: 119852
 2010-11-19 22:14:31 +00:00
Jim Grosbach 6e9aace4f3 Factor out operand encoding bits for ARM addressing mode 2 store instructions. 
llvm-svn: 119846
 2010-11-19 21:35:06 +00:00
Jim Grosbach 09f6823eb6 Delete another dead class. 
llvm-svn: 119844
 2010-11-19 21:16:08 +00:00
Jim Grosbach e093e5f0dc whitespace tweak. 
llvm-svn: 119843
 2010-11-19 21:14:37 +00:00
Jim Grosbach d6e5c9f2fe Refactor PICSTR* instructions to really be pseudos. Nuke dead classes. 
llvm-svn: 119841
 2010-11-19 21:14:02 +00:00
Jim Grosbach 4a22eba616 Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes. 
llvm-svn: 119840
 2010-11-19 21:07:51 +00:00
Jim Grosbach 003c6e700b Add ARM binary encoding information for the rest of the indexed loads. 
llvm-svn: 119821
 2010-11-19 19:41:26 +00:00
Jim Grosbach c6ac246671 Remove dead code. 
llvm-svn: 119815
 2010-11-19 18:18:37 +00:00
Jim Grosbach 76aed40813 ARM LDRD binary encoding. 
llvm-svn: 119812
 2010-11-19 18:16:46 +00:00
Jim Grosbach 1b91ae18ed Add ARM encoding information for LDRH post-increment. 
llvm-svn: 119743
 2010-11-18 21:43:37 +00:00
Owen Anderson 3625098459 Fill out the set of Thumb2 multiplication operator encodings. 
llvm-svn: 119733
 2010-11-18 20:32:18 +00:00
Jim Grosbach 51fdc47a11 ARMPseudoInst instructions should default to being considered a single 4-byte 
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274

llvm-svn: 119713
 2010-11-18 18:01:40 +00:00
Jim Grosbach a74c7ccd59 ARM PseudoInst instructions don't need or use an assembler string. Get rid of 
the operand to the pattern.

llvm-svn: 119607
 2010-11-18 01:38:26 +00:00
Jim Grosbach 19be1fbca1 Add FIXME. 
llvm-svn: 119603
 2010-11-18 01:20:48 +00:00
Jim Grosbach cfb66204b7 Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not 
just pretend to be.

llvm-svn: 119602
 2010-11-18 01:15:56 +00:00
Jim Grosbach 8e7f8df4a2 Refactor a few ARM load instructions to better parameterize things and re-use 
common encoding information.

llvm-svn: 119598
 2010-11-18 00:46:58 +00:00
Jim Grosbach 8839775df6 More ARM encoding bits. LDRH now encodes properly. 
llvm-svn: 119529
 2010-11-17 18:11:11 +00:00
Bill Wendling 345b48fcbd Add binary emission stuff for VLDM/VSTM. This reuses the 
"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.

llvm-svn: 119435
 2010-11-17 00:45:23 +00:00
Bill Wendling 3bd60eff26 - Remove dead patterns. 
- Add encodings to the *LDMIA_RET instrs. Probably not needed...

llvm-svn: 119323
 2010-11-16 02:08:45 +00:00
Jim Grosbach 38b469effd ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding. 
llvm-svn: 119180
 2010-11-15 20:47:07 +00:00
Chris Lattner 63274cbc5d add fields to the .td files unconditionally, simplifying tblgen a bit. 
Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120
 2010-11-15 05:19:05 +00:00
Bill Wendling e69afc6bb7 Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the 
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.

llvm-svn: 118995
 2010-11-13 09:09:38 +00:00
Jim Grosbach 2f790749e8 More ARM load/store indexed refactoring. Also fix an incorrect IndexMode 
flag for the LDRT/STRT family instructions as a side effect.

llvm-svn: 118955
 2010-11-13 00:35:48 +00:00
Jim Grosbach 31a7234a47 Refactor to parameterize some ARM load/store encoding patterns. Preparatory 
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.

llvm-svn: 118925
 2010-11-12 21:28:15 +00:00
Evan Cheng 2d59ee34f1 Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next. 
llvm-svn: 118922
 2010-11-12 20:32:20 +00:00
Jim Grosbach 6bb1ae9d45 Kill more unused stuff. 
llvm-svn: 118921
 2010-11-12 19:27:45 +00:00
Jim Grosbach 984ff7d17e Remove unused class. 
llvm-svn: 118919
 2010-11-12 19:24:53 +00:00
Jim Grosbach 0deb9c20c0 Encoding for ARM LDRSB instructions. 
llvm-svn: 118905
 2010-11-12 17:52:59 +00:00
Owen Anderson ce2250fba4 Fill out support for Thumb2 encodings of NEON instructions. 
llvm-svn: 118854
 2010-11-11 23:12:55 +00:00
Owen Anderson 99a8cb4875 Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. 
llvm-svn: 118843
 2010-11-11 21:36:43 +00:00
Owen Anderson 7ffe3b35ac Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. 
More tests to come.

llvm-svn: 118819
 2010-11-11 19:07:48 +00:00
Jim Grosbach 68685e644f Encoding for ARM LDRSH_POST. 
llvm-svn: 118794
 2010-11-11 16:55:29 +00:00
Jim Grosbach f18b951e18 Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names. 
llvm-svn: 118767
 2010-11-11 01:55:59 +00:00
Jim Grosbach 607efcbc3e ARM STRH encoding information. 
llvm-svn: 118757
 2010-11-11 01:09:40 +00:00
Jim Grosbach c4dd2349c7 Move LDM predicate operand encoding into base clase. Add STM missing STM 
encoding bits.

llvm-svn: 118738
 2010-11-10 23:44:32 +00:00
Jim Grosbach cc4a491557 ARM LDM encoding for the mode (ia, ib, da, db) operand. 
llvm-svn: 118736
 2010-11-10 23:38:36 +00:00
Jim Grosbach 58ef598cd1 Fix ARM encoding of non-return LDM instructions. 
llvm-svn: 118732
 2010-11-10 23:18:49 +00:00
Jim Grosbach e39a9fcc0e Fix ARM encoding of LDM+Return instruction. 
llvm-svn: 118730
 2010-11-10 23:12:48 +00:00
Bill Wendling c002463ac4 Add encoding for VSTR. 
llvm-svn: 118220
 2010-11-04 00:59:42 +00:00
Owen Anderson 0ebd1fd594 Revert r118097 to fix buildbots. 
llvm-svn: 118121
 2010-11-02 23:47:29 +00:00
Owen Anderson 7c30390277 Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning. 
llvm-svn: 118097
 2010-11-02 22:41:42 +00:00
Owen Anderson 9f20daf3b4 Factor out a common encoding class for loads and stores with a lane parameter. 
llvm-svn: 118055
 2010-11-02 20:47:39 +00:00
Owen Anderson ad40234eff Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Bill Wendling 418bd53008 Move the machine operand MC encoding patterns to the parent classes. 
llvm-svn: 117956
 2010-11-01 21:17:06 +00:00
Jim Grosbach fddf36d254 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Bill Wendling 2623343625 Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
 2010-11-01 06:00:39 +00:00