Commit Graph

152 Commits

Author SHA1 Message Date
Evan Cheng 244183ef0d commuteInstr() can now commute non-ssa machine instrs.
llvm-svn: 47043
2008-02-13 02:46:49 +00:00
Evan Cheng 3b3286d4bc It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
llvm-svn: 46893
2008-02-08 21:20:40 +00:00
Evan Cheng 8d59dd119b Added missing entries in X86 load / store folding tables.
llvm-svn: 46866
2008-02-08 00:12:56 +00:00
Evan Cheng 1bc1cae318 In some cases, e.g. ADD32ri, no transformation is made. Guide against it.
llvm-svn: 46849
2008-02-07 08:29:53 +00:00
Chris Lattner 18df33d0c8 fix a wordo that gordon noticed :)
llvm-svn: 45896
2008-01-12 00:53:16 +00:00
Chris Lattner 6da61c2515 Any x86 instruction that reads from an invariant location is invariant.
This allows us to sink things like:
	cvtsi2sd	32(%esp), %xmm1
when reading from the argument area, for example.

llvm-svn: 45895
2008-01-12 00:35:08 +00:00
Chris Lattner 596875118c rename MachineInstr::setInstrDescriptor -> setDesc
llvm-svn: 45871
2008-01-11 18:10:50 +00:00
Chris Lattner 806dd0e2ac remove xchg and shift-reg-by-1 instructions, which are dead.
llvm-svn: 45870
2008-01-11 18:00:50 +00:00
Chris Lattner c8226f32e9 Simplify the side effect stuff a bit more and make licm/sinking
both work right according to the new flags.

This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad. 

It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags.  Now the clients
can decide everything they need.

I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.

llvm-svn: 45843
2008-01-10 23:08:24 +00:00
Chris Lattner f171482a66 verify that the frame index is immutable before remat'ing (still disabled)
or being side-effect free.

llvm-svn: 45816
2008-01-10 04:16:31 +00:00
Chris Lattner 9129f51f9b add a testcase
llvm-svn: 45768
2008-01-09 00:37:18 +00:00
Bill Wendling a3bdad153f Operand 1 should be a register. We don't care if it's a preg, vreg, or 0.
llvm-svn: 45699
2008-01-07 08:05:29 +00:00
Chris Lattner 03ad885039 rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
2008-01-07 07:27:27 +00:00
Chris Lattner b0d06b4381 Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
llvm-svn: 45680
2008-01-07 03:13:06 +00:00
Chris Lattner f0f438a517 remove MachineOpCode typedef.
llvm-svn: 45679
2008-01-07 02:48:55 +00:00
Chris Lattner e55e115616 Add predicates methods to TargetOperandInfo, and switch all clients
over to using them, instead of diddling Flags directly.  Change the
various flags from const variables to enums.

llvm-svn: 45677
2008-01-07 02:39:19 +00:00
Chris Lattner a98c679de0 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674
2008-01-07 01:56:04 +00:00
Owen Anderson 2a3be7bb6c Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...

llvm-svn: 45672
2008-01-07 01:35:02 +00:00
Bill Wendling 5fa2c64b78 Fix comment.
llvm-svn: 45638
2008-01-05 23:30:51 +00:00
Bill Wendling be984cf10b Chris and Evan noticed that this check was compleatly fubared. I was
checking that there was a from a global instead of a load from the stub
for a global, which is the one that's safe to hoist.

Consider this program:

volatile char G[100];
int B(char *F, int N) {
  for (; N > 0; --N)
    F[N] = G[N];
}

In static mode, we shouldn't be hoisting the load from G:

$ llc -relocation-model=static -o - a.bc -march=x86 -machine-licm

LBB1_1: # bb.preheader
        leal    -1(%eax), %edx
        testl   %edx, %edx
        movl    $1, %edx
        cmovns  %eax, %edx
        xorl    %esi, %esi
LBB1_2: # bb
        movb    _G(%eax), %bl
        movb    %bl, (%ecx,%eax)

llvm-svn: 45626
2008-01-05 09:18:04 +00:00
Chris Lattner e0f0c4aa02 enable sinking and licm of loads from the argument area. I'd like to enable this
for remat, but can't due to an RA bug.

llvm-svn: 45623
2008-01-05 06:10:42 +00:00
Chris Lattner d4738ee8e1 simplify some code by using shorter accessors.
llvm-svn: 45622
2008-01-05 05:28:30 +00:00
Chris Lattner 86f4a2e4f2 revert my previous patch.
llvm-svn: 45621
2008-01-05 05:26:26 +00:00
Chris Lattner 69d7902cf1 factor some code better to avoid redundancy between
isReallySideEffectFree and isReallyTriviallyReMaterializable.  Why is a load from
a global considered side-effect-free but not rematable?

llvm-svn: 45620
2008-01-05 05:19:56 +00:00
Owen Anderson 6bb0c52628 Move some more functionality from MRegisterInfo to TargetInstrInfo.
llvm-svn: 45603
2008-01-04 23:57:37 +00:00
Bill Wendling e1f28e7871 Machine LICM will check that operands are defined outside of the loop. Also
check that register isn't 0 before going further.

llvm-svn: 45498
2008-01-02 21:10:40 +00:00
Owen Anderson eee14601b1 Move some more instruction creation methods from RegisterInfo into InstrInfo.
llvm-svn: 45484
2008-01-01 21:11:32 +00:00
Chris Lattner b0fb17fd34 Fix a bug in my previous patch: refer to the impl not the pure virtual version. It's unclear why gcc would ever compile this...
llvm-svn: 45476
2008-01-01 01:05:34 +00:00
Chris Lattner 25568e4cef Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.

llvm-svn: 45475
2008-01-01 01:03:04 +00:00
Owen Anderson 7a73ae9a86 Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.

llvm-svn: 45470
2007-12-31 06:32:00 +00:00
Chris Lattner a10fff51d9 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467
2007-12-31 04:13:23 +00:00
Chris Lattner a5bb370aa4 Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464
2007-12-30 23:10:15 +00:00
Chris Lattner 5c4637816e Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
llvm-svn: 45453
2007-12-30 20:49:49 +00:00
Bill Wendling 7749a9014b If we have a load of a global address that's not modified during the
function, then go ahead and hoist it out of the loop. This is the result:

$ cat a.c
volatile int G;

int A(int N) {
  for (; N > 0; --N)
    G++;
}
$ llc -o - -relocation-model=pic
_A:
...
LBB1_2: # bb
        movl    L_G$non_lazy_ptr-"L1$pb"(%eax), %esi
        incl    (%esi)
        incl    %edx
        cmpl    %ecx, %edx
        jne     LBB1_2  # bb
...
$ llc -o - -relocation-model=pic -machine-licm
_A:
...
        movl    L_G$non_lazy_ptr-"L1$pb"(%eax), %eax
LBB1_2: # bb
        incl    (%eax)
        incl    %edx
        cmpl    %ecx, %edx
        jne     LBB1_2  # bb
...

I'm limiting this to the MOV32rm x86 instruction for now.

llvm-svn: 45444
2007-12-30 03:18:58 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Bill Wendling b3d85a5d4b Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I
based what flag to set on whether it was already marked as
"isRematerializable". If there was a further check to determine if it's "really"
rematerializable, then I marked it as "mayHaveSideEffects" and created a check
in the X86 back-end similar to the remat one.

llvm-svn: 45132
2007-12-17 23:07:56 +00:00
Bill Wendling 3f19dfe794 Reverting 44702. It wasn't correct to rename them.
llvm-svn: 44727
2007-12-08 23:58:46 +00:00
Bill Wendling 2b07d8c5a0 Renaming:
isTriviallyReMaterializable -> hasNoSideEffects
  isReallyTriviallyReMaterializable -> isTriviallyReMaterializable

llvm-svn: 44702
2007-12-08 07:17:56 +00:00
Arnold Schwaighofer 9ccea99165 Added tail call optimization to the x86 back end. It can be
enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870
2007-10-11 19:40:01 +00:00
Evan Cheng 82bc90ac60 Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte.
llvm-svn: 42783
2007-10-09 07:14:53 +00:00
Evan Cheng 18109c88c3 Allow x86 compare to be commutable by default.
llvm-svn: 42761
2007-10-08 18:27:46 +00:00
Evan Cheng 1151ffde70 Commute x86 cmove instructions by swapping the operands and change the condition
to its inverse.
Testing this as llcbeta

llvm-svn: 42661
2007-10-05 23:13:21 +00:00
Evan Cheng 484cab7a2f Enable convertToThreeAddress for X86 by default.
llvm-svn: 42655
2007-10-05 22:31:10 +00:00
Evan Cheng d3ccf00870 INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still can
cause performance degradation.

llvm-svn: 42653
2007-10-05 21:55:32 +00:00
Evan Cheng fa2c828687 In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g.
leal 1(%ecx), %edi, which requires 67H prefix.

llvm-svn: 42647
2007-10-05 20:34:26 +00:00
Evan Cheng aac0f8e351 Add support to convert more 64-bit instructions to 3-address instructions.
llvm-svn: 42642
2007-10-05 18:20:36 +00:00
Evan Cheng a8a9c15e30 Testing convertToThreeeAddress as X86 llcbeta.
llvm-svn: 42630
2007-10-05 08:04:01 +00:00
Evan Cheng 5fb5a1f389 Enabling new condition code modeling scheme.
llvm-svn: 42459
2007-09-29 00:00:36 +00:00
Evan Cheng e95f391ef1 Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
all the kinks are worked out.

llvm-svn: 42285
2007-09-25 01:57:46 +00:00
Dan Gohman 3243e10ef0 Add 64-bit jmp instructions to the list of instructions that
can terminate a block with no fall-through.

llvm-svn: 42029
2007-09-17 15:19:08 +00:00