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21 Commits

Author SHA1 Message Date
Tom Stellard 10b1502733 R600/SI: Add processor type for Mullins. 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
llvm-svn: 207846
 2014-05-02 15:41:49 +00:00
Tom Stellard 348273df97 R600: Recommit 199842: Add work-around for the CF stack entry HW bug 
The unit test is now disabled on non-asserts builds.

The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE,
CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of
sub-entries on the stack is greater than or equal to the stack entry
size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is
present when number of sub-entries module 8 is either 7 or 0)

We choose to be conservative and always apply the work-around when the
number of sub-enries is greater than or equal to the stack entry size,
so that we can safely over-allocate the stack when we are unsure of the
stack allocation rules.

reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 199905
 2014-01-23 16:18:02 +00:00
Tom Stellard 31e16388d7 Revert "R600: Add work-around for the CF stack entry HW bug" 
This reverts commit 35b8331cad6eb512a2506adbc394201181da94ba.

The -debug-only flag for llc doesn't appear to be available in
all build configurations.

llvm-svn: 199845
 2014-01-22 22:20:54 +00:00
Tom Stellard e89373e062 R600: Add work-around for the CF stack entry HW bug 
The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE,
CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of
sub-entries on the stack is greater than or equal to the stack entry
size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is
present when number of sub-entries module 8 is either 7 or 0)

We choose to be conservative and always apply the work-around when the
number of sub-enries is greater than or equal to the stack entry size,
so that we can safely over-allocate the stack when we are unsure of the
stack allocation rules.

reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 199842
 2014-01-22 21:55:46 +00:00
Tom Stellard 8c347b024e R600: Add wavefront size property to the subtargets v2 
v2:
  - Initialize wavefront size to 0

reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 199838
 2014-01-22 21:55:40 +00:00
Tom Stellard d7e146ede6 R600: Re-format Processors.td 
This makes it a little easier to read.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 197058
 2013-12-11 17:51:51 +00:00
Tom Stellard 81229a14a3 R600/SI: Add processor type for Hawaii 
Patch by: Alex Deucher

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
llvm-svn: 194752
 2013-11-14 23:46:00 +00:00
Tom Stellard 6e1ee476ab R600/SI: Add compute support for CI v2 
v2:
  - Fix LDS size calculation

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 193621
 2013-10-29 16:37:28 +00:00
Chad Rosier 797ee3e3c6 Add a newline. 
llvm-svn: 185385
 2013-07-01 21:31:10 +00:00
Tom Stellard c46e56721e R600/SI: Add processor types for each CIK variant 
Patch By: Alex Deucher

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
llvm-svn: 185209
 2013-06-28 20:23:29 +00:00
Tom Stellard a6c6e1bfc2 R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183566
 2013-06-07 20:37:48 +00:00
Tom Stellard 3498e4ff1d R600: Fix the fetch limits for R600 generation GPUs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 183560
 2013-06-07 20:28:55 +00:00
Tom Stellard 1e21b53020 R600/SI: Add processor type for Hainan asic 
Patch by: Alex Deucher

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181792
 2013-05-14 14:42:56 +00:00
Tom Stellard c2516c6e40 R600: Clean up comments in Processors.td 
llvm-svn: 181032
 2013-05-03 17:21:14 +00:00
Vincent Lejeune 076c0b28e3 R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips 
llvm-svn: 180759
 2013-04-30 00:14:17 +00:00
Vincent Lejeune c299164284 R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions 
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

llvm-svn: 180755
 2013-04-30 00:13:39 +00:00
Vincent Lejeune 7d820c0bef R600: Add some new processor variants 
llvm-svn: 180753
 2013-04-30 00:13:27 +00:00
Tom Stellard 60174bb9ca R600: Add RV670 processor 
This is an R600 GPU with double support.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178929
 2013-04-05 23:31:40 +00:00
Tom Stellard 2f21c7e551 R600/SI: Add processor types for each SI variant 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178928
 2013-04-05 23:31:35 +00:00
Tom Stellard 4ded0c1c42 R600: Add an explicit default processor 
This is for the case when no processor is passed to the backend.  This
prevents the

'' is not a recognized processor for this target (ignoring processor)

warning from being generated by clang.

llvm-svn: 174651
 2013-02-07 19:39:34 +00:00
Tom Stellard 75aadc2813 Add R600 backend 
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

llvm-svn: 169915
 2012-12-11 21:25:42 +00:00