2 Commits

Author	SHA1	Message	Date
Danilo Carvalho Grael	db9c40f562	[AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations ... Summary: Add intrinsics for the following operations: - eor3, bcax - bsl, bsl1n, bsl2n, nbsl Fix MC tests for bsl instructions. Reviewers: kmclaughlin, c-rhodes, sdesmalen, efriedma, rengolin Reviewed By: efriedma Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74785	2020-02-21 12:15:51 -05:00
Cullen Rhodes	6c04ef3d48	[AArch64][SVE2] Asm: support SVE Bitwise Logical - Unpredicated Group ... Summary: Patch adds support for the following instructions: * EOR3, BSL, BCAX, BSL1N, BSL2N, NBSL, XAR Aliases for types .B/.H/.S for EOR3 and BCAX have been added, the preferred disassembly is .D. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62387 llvm-svn: 361936	2019-05-29 09:03:27 +00:00