Commit Graph

150 Commits

Author SHA1 Message Date
Evan Cheng c288cc0572 ldm / stm instruction encodings.
llvm-svn: 55599
2008-09-01 07:48:18 +00:00
Evan Cheng c37532b24a AXI2 and AXI3 instruction encodings.
llvm-svn: 55598
2008-09-01 07:34:13 +00:00
Evan Cheng 169eccc24e addrmode3 instruction encodings.
llvm-svn: 55596
2008-09-01 07:00:14 +00:00
Evan Cheng cccca875b1 Rest of addrmode2 instruction encodings.
llvm-svn: 55593
2008-09-01 01:27:33 +00:00
Evan Cheng 01fd3f129a Addr2 word / byte load encodings.
llvm-svn: 55591
2008-08-31 19:02:21 +00:00
Evan Cheng 9f717afd68 MVN is addrmode1.
llvm-svn: 55530
2008-08-29 07:36:24 +00:00
Evan Cheng 2d37f19ef2 Refactor ARM instruction format definitions into a separate file. No functionality changes.
llvm-svn: 55518
2008-08-28 23:39:26 +00:00
Dan Gohman 2ce6f2ad5e Rename SDOperand to SDValue.
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
Evan Cheng 0e7b00d79f Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Bill Wendling 97925ec704 Final de-tabification.
llvm-svn: 47663
2008-02-27 06:33:05 +00:00
Chris Lattner 1ea55cf816 This commit changes:
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret

llvm-svn: 46140
2008-01-17 19:59:44 +00:00
Chris Lattner 9a249b0ce5 rename SDTRet -> SDTNone.
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
2008-01-15 22:02:54 +00:00
Chris Lattner 94de7bc3aa get def use info more correct.
llvm-svn: 45821
2008-01-10 05:12:37 +00:00
Evan Cheng 7250120177 Only mark instructions that load a single value without extension as isSimpleLoad = 1.
llvm-svn: 45727
2008-01-07 23:56:57 +00:00
Chris Lattner a4ce4f6987 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
llvm-svn: 45667
2008-01-06 23:38:27 +00:00
Chris Lattner 10324d0175 rename isStore -> mayStore to more accurately reflect what it captures.
llvm-svn: 45656
2008-01-06 08:36:04 +00:00
Chris Lattner f4d55ec4e8 remove explicit isStore flags that are now inferrable.
llvm-svn: 45653
2008-01-06 05:55:01 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Evan Cheng 6e68381e02 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
llvm-svn: 44960
2007-12-12 23:12:09 +00:00
Bill Wendling 77b13af9a6 Unifacalize the CALLSEQ{START,END} stuff.
llvm-svn: 44045
2007-11-13 09:19:02 +00:00
Bill Wendling f359fed9f9 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037
2007-11-13 00:44:25 +00:00
Owen Anderson 933b5b7e62 Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
2007-11-12 07:39:39 +00:00
Evan Cheng 3e18e504ae Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
llvm-svn: 41863
2007-09-11 19:55:27 +00:00
Evan Cheng f948772f9e 80 col.
llvm-svn: 41812
2007-09-10 22:22:23 +00:00
Raul Herbster 73489273ae ARM instruction table was modified by adding information to generate multiply instruction of V5TE.
llvm-svn: 41626
2007-08-30 23:25:47 +00:00
Evan Cheng f7c6effc44 Initial JIT support for ARM by Raul Fernandes Herbster.
llvm-svn: 40887
2007-08-07 01:37:15 +00:00
Evan Cheng aa39b39eec Indexed loads each has 2 outputs.
llvm-svn: 40658
2007-08-01 00:12:08 +00:00
Evan Cheng ac1591be42 No more noResults.
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Evan Cheng 9d41b311fb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
Evan Cheng 881248c4e1 No need for ccop anymore.
llvm-svn: 37965
2007-07-06 23:34:09 +00:00
Evan Cheng 76a97c5f8a Do away with ImmutablePredicateOperand.
llvm-svn: 37961
2007-07-06 23:22:46 +00:00
Evan Cheng 5c66888580 PredicateDefOperand -> OptionalDefOperand.
llvm-svn: 37931
2007-07-06 01:00:49 +00:00
Evan Cheng 085314b455 Unbreak the build.
llvm-svn: 37914
2007-07-05 17:13:19 +00:00
Evan Cheng aa3b8014bd Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
llvm-svn: 37895
2007-07-05 07:13:32 +00:00
Dan Gohman e8c1e428f2 Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Owen Anderson 0c550df9d2 Fix the build.
llvm-svn: 37705
2007-06-22 16:59:54 +00:00
Evan Cheng c3c949b473 Allow predicated immediate ARM to ARM calls.
llvm-svn: 37659
2007-06-19 21:05:09 +00:00
Dan Gohman 9e82064924 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng a7ca624028 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
Evan Cheng e8c3cbf971 Mark these instructions clobbersPred. They modify the condition code register.
llvm-svn: 37468
2007-06-06 10:17:05 +00:00
Evan Cheng 9aa5fc8577 Opcode modifier s comes after condition code. e.g. addlts, not addslt.
llvm-svn: 37388
2007-06-01 20:51:29 +00:00
Evan Cheng a2ab4e5feb Make jumptable non-predicable for now.
llvm-svn: 37381
2007-06-01 00:56:15 +00:00
Evan Cheng a6e9a4ce07 For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq.
llvm-svn: 37349
2007-05-29 23:32:06 +00:00
Dale Johannesen d1de276c16 Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
llvm-svn: 37271
2007-05-21 22:42:04 +00:00
Dale Johannesen 7d55f3733e Add some patterns for PIC PC-relative loads and stores.
llvm-svn: 37269
2007-05-21 22:14:33 +00:00
Evan Cheng 4ae1840d21 Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.
llvm-svn: 37199
2007-05-18 01:53:54 +00:00
Evan Cheng dcd6cdf896 Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
llvm-svn: 37118
2007-05-16 20:50:01 +00:00
Evan Cheng 01a4227ed1 Conditional branch is not a barrier.
llvm-svn: 37103
2007-05-16 07:45:54 +00:00
Evan Cheng 0f7cbe8370 Add PredicateOperand to all ARM instructions that have the condition field.
llvm-svn: 37066
2007-05-15 01:29:07 +00:00