c288cc0572
ldm / stm instruction encodings.
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llvm-svn: 55599
2008-09-01 07:48:18 +00:00
c37532b24a
AXI2 and AXI3 instruction encodings.
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llvm-svn: 55598
2008-09-01 07:34:13 +00:00
a282723499
Reorganize instruction formats again; AXI1 encoding.
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llvm-svn: 55597
2008-09-01 07:19:00 +00:00
169eccc24e
addrmode3 instruction encodings.
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llvm-svn: 55596
2008-09-01 07:00:14 +00:00
624844b4dd
Reorganize some instruction format definitions. No functionality change.
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llvm-svn: 55594
2008-09-01 01:51:14 +00:00
cccca875b1
Rest of addrmode2 instruction encodings.
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llvm-svn: 55593
2008-09-01 01:27:33 +00:00
01fd3f129a
Addr2 word / byte load encodings.
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llvm-svn: 55591
2008-08-31 19:02:21 +00:00
5b6c931e1f
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
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llvm-svn: 55590
2008-08-31 18:32:16 +00:00
81d6a38434
fix a bunch of 80-col violations
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llvm-svn: 55588
2008-08-31 15:37:04 +00:00
aebd2662d3
Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR
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instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
llvm-svn: 55582
2008-08-31 02:59:23 +00:00
62cf24343c
Expand for ROTR with MVT::i64.
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Dale, Could you please review this?
llvm-svn: 55581
2008-08-31 02:53:19 +00:00
a719239719
fix some 80-col violations
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llvm-svn: 55565
2008-08-30 10:09:02 +00:00
b8d588d89c
For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.
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llvm-svn: 55562
2008-08-30 08:54:22 +00:00
cfb7f3abdf
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
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llvm-svn: 55558
2008-08-30 02:03:58 +00:00
340d264f52
Add ppc partial-word ATOMIC_CMP_SWAP.
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llvm-svn: 55554
2008-08-30 00:08:53 +00:00
3fddc7e906
Swap fp comparison operands and change predicate to allow load folding (safely this time).
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llvm-svn: 55553
2008-08-29 23:22:12 +00:00
f93bc7f755
Use static_cast instead of C style cast.
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llvm-svn: 55552
2008-08-29 23:21:31 +00:00
b3ed09703c
Backing out 55521. Not safe.
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llvm-svn: 55548
2008-08-29 22:13:21 +00:00
f0a88d6b2a
Add partial word version of ATOMIC_SWAP.
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llvm-svn: 55546
2008-08-29 18:29:46 +00:00
0673a8af14
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
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llvm-svn: 55545
2008-08-29 17:45:56 +00:00
44b2138b9a
TableGen'ing instruction encodings.
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llvm-svn: 55533
2008-08-29 07:42:03 +00:00
c139c221dd
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
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llvm-svn: 55531
2008-08-29 07:40:52 +00:00
9f717afd68
MVN is addrmode1.
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llvm-svn: 55530
2008-08-29 07:36:24 +00:00
ee98fa9db2
More refactoring.
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llvm-svn: 55528
2008-08-29 06:41:12 +00:00
960b17a3c2
Swap fp comparison operands and change predicate to allow load folding.
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llvm-svn: 55521
2008-08-28 23:48:31 +00:00
2d37f19ef2
Refactor ARM instruction format definitions into a separate file. No functionality changes.
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llvm-svn: 55518
2008-08-28 23:39:26 +00:00
d58f3e36d0
Add a target callback for FastISel.
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llvm-svn: 55512
2008-08-28 23:21:34 +00:00
95d77f5466
remove tabs, fix > 80 cols
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llvm-svn: 55511
2008-08-28 23:19:51 +00:00
f304a7aa4d
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
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llvm-svn: 55504
2008-08-28 21:40:38 +00:00
1e137300bd
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
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llvm-svn: 55499
2008-08-28 21:04:05 +00:00
26d54b3ef3
Use resize instead of reserve. Reserve doesn't change size().
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llvm-svn: 55486
2008-08-28 18:32:53 +00:00
a32affb9ba
Implement partial-word binary atomics on ppc.
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llvm-svn: 55478
2008-08-28 17:53:09 +00:00
97af20f85f
FsFLD0S{S|D} and V_SETALLONES are as cheap as moves.
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llvm-svn: 55466
2008-08-28 07:52:25 +00:00
41be0d4445
Split the ATOMIC NodeType's to include the size, e.g.
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ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.
This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad. This is the alternative.
llvm-svn: 55457
2008-08-28 02:44:49 +00:00
76105a4a4f
Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the
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SSE2 registers as well as the MMX registers.
llvm-svn: 55436
2008-08-27 21:32:04 +00:00
7f2777e8d2
Reinstate the x86-64 portion of r55190. When doing extloads into
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64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.
llvm-svn: 55422
2008-08-27 17:33:15 +00:00
abfdf928d8
disallow direct access to SDValue::ResNo, provide a getter instead
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llvm-svn: 55394
2008-08-26 22:36:50 +00:00
42ccd39689
These assertions should be return false's instead, allowing the client to detect the failure.
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llvm-svn: 55377
2008-08-26 18:50:40 +00:00
27fb3dcbc7
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
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was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
llvm-svn: 55375
2008-08-26 18:03:31 +00:00
09f8cef571
If an xmm register is referenced explicitly in an inline asm, make sure to
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assign it to a version of the xmm register with the regclass that matches its
type. This fixes PR2715, a bug handling some crazy xpcom case in mozilla.
llvm-svn: 55358
2008-08-26 06:19:02 +00:00
4884f87822
This is done.
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llvm-svn: 55348
2008-08-26 01:13:44 +00:00
d4eb0521e4
Implement 32 & 64 bit versions of PPC atomic
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binary primitives.
llvm-svn: 55343
2008-08-25 22:34:37 +00:00
2da2e65d7d
80 col. violations.
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llvm-svn: 55341
2008-08-25 21:58:43 +00:00
f00f1e50b5
Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
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llvm-svn: 55338
2008-08-25 21:27:18 +00:00
765065c982
Remove PPC-specific lowering for atomics; the
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generic stuff works fine.
Mark rewritten cmp-and-swap as not using CR1.
llvm-svn: 55336
2008-08-25 21:09:52 +00:00
166d6cb1fa
It's important for the cmp-and-swap to balance
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loads and stores but it's even more important for
it to store the right value.:(
llvm-svn: 55319
2008-08-25 18:53:26 +00:00
6cfd3830fb
Nevermind. This broke the bootstrap (?!).
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llvm-svn: 55318
2008-08-25 18:32:39 +00:00
dd6759aea7
MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these
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instructions on having SSE2.
llvm-svn: 55317
2008-08-25 18:20:52 +00:00
e414681352
Fix asm printing of MOVSDto64mr and MOV64toSDrm.
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llvm-svn: 55300
2008-08-25 04:11:42 +00:00
5b836c5f77
Temporarily reverting r55292. It's causing a bootstraping failure:
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/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2
llvm-svn: 55295
2008-08-24 21:45:30 +00:00
Evan Cheng