c288cc0572
ldm / stm instruction encodings.
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llvm-svn: 55599
2008-09-01 07:48:18 +00:00
c37532b24a
AXI2 and AXI3 instruction encodings.
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llvm-svn: 55598
2008-09-01 07:34:13 +00:00
a282723499
Reorganize instruction formats again; AXI1 encoding.
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llvm-svn: 55597
2008-09-01 07:19:00 +00:00
169eccc24e
addrmode3 instruction encodings.
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llvm-svn: 55596
2008-09-01 07:00:14 +00:00
624844b4dd
Reorganize some instruction format definitions. No functionality change.
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llvm-svn: 55594
2008-09-01 01:51:14 +00:00
cccca875b1
Rest of addrmode2 instruction encodings.
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llvm-svn: 55593
2008-09-01 01:27:33 +00:00
01fd3f129a
Addr2 word / byte load encodings.
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llvm-svn: 55591
2008-08-31 19:02:21 +00:00
5b6c931e1f
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
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llvm-svn: 55590
2008-08-31 18:32:16 +00:00
81d6a38434
fix a bunch of 80-col violations
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llvm-svn: 55588
2008-08-31 15:37:04 +00:00
aebd2662d3
Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR
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instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
llvm-svn: 55582
2008-08-31 02:59:23 +00:00
62cf24343c
Expand for ROTR with MVT::i64.
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Dale, Could you please review this?
llvm-svn: 55581
2008-08-31 02:53:19 +00:00
58bb4f1bf0
Cosmetic changes to Machine LICM. No functionality change.
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llvm-svn: 55578
2008-08-31 02:30:23 +00:00
11284ea499
Another situation where ROTR is cheaper than ROTL.
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llvm-svn: 55577
2008-08-31 01:13:31 +00:00
4822a7ac8a
For this pattern, ROTR is the cheaper option.
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llvm-svn: 55576
2008-08-31 01:04:56 +00:00
fc72416447
- Fix comment so that it describes how the code really works:
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// fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
// (rotl x, y)
// fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
// (rotr x, (sub 32, y))
Example: (x == 0xDEADBEEF and y == 4)
(x << 4) | (x >> 28)
=> 0xEADBEEF0 | 0x0000000D
=> 0xEADBEEFD
(rotl x, 4)
=> 0xEADBEEFD
(rotr x, 28)
=> 0xEADBEEFD
- Fix comment and code for second version. It wasn't using the rot* propertly.
// fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
// (rotr x, y)
// fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
// (rotl x, (sub 32, y))
(x << 28) | (x >> 4)
=> 0xD0000000 | 0x0DEADBEE
=> 0xDDEADBEE
(rotl x, 4)
=> 0xEADBEEFD
(rotr x, 28)
=> (0xEADBEEFD)
llvm-svn: 55575
2008-08-31 00:37:27 +00:00
66ccf603a9
typo
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llvm-svn: 55574
2008-08-30 22:16:05 +00:00
e12264bf41
fix some 80-col violations
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llvm-svn: 55571
2008-08-30 19:29:20 +00:00
eeb6537abb
PR2731: C and Ocaml bindings for setTailCall and isTailCall.
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Based on patch by Giorgos Korfiatis.
llvm-svn: 55570
2008-08-30 16:34:54 +00:00
b52d1ed7e9
Fix ConstantExpr::getInsertElement.
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Breakage was exposed in the Ocaml bindings tests after Chris
uncommented an assertion in r55084.
llvm-svn: 55566
2008-08-30 15:41:51 +00:00
a719239719
fix some 80-col violations
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llvm-svn: 55565
2008-08-30 10:09:02 +00:00
a3771d5bd9
Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.
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llvm-svn: 55564
2008-08-30 09:09:33 +00:00
542ac62971
Fold isRematerializable checks into isSafeToReMat.
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llvm-svn: 55563
2008-08-30 09:07:18 +00:00
b8d588d89c
For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.
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llvm-svn: 55562
2008-08-30 08:54:22 +00:00
cfb7f3abdf
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
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llvm-svn: 55558
2008-08-30 02:03:58 +00:00
6f0c51d9da
Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg
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assignment when selecting the def. This is the naive solution to the problem: insert a copy to the pre-chosen
vreg. Other solutions might be preferable, such as:
1) Passing the dest reg into FastEmit_. However, this would require the higher level code to know about reg classes, which they don't currently.
2) Selecting blocks in reverse postorder. This has some compile time cost for computing the order, and we'd need to measure its impact.
llvm-svn: 55555
2008-08-30 00:38:46 +00:00
340d264f52
Add ppc partial-word ATOMIC_CMP_SWAP.
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llvm-svn: 55554
2008-08-30 00:08:53 +00:00
3fddc7e906
Swap fp comparison operands and change predicate to allow load folding (safely this time).
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llvm-svn: 55553
2008-08-29 23:22:12 +00:00
f93bc7f755
Use static_cast instead of C style cast.
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llvm-svn: 55552
2008-08-29 23:21:31 +00:00
894be333f1
Fix 80 col. violations.
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llvm-svn: 55551
2008-08-29 23:20:46 +00:00
5e7658c2e4
Back out 55498. It broken Apple style bootstrapping.
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llvm-svn: 55549
2008-08-29 22:21:44 +00:00
b3ed09703c
Backing out 55521. Not safe.
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llvm-svn: 55548
2008-08-29 22:13:21 +00:00
f0a88d6b2a
Add partial word version of ATOMIC_SWAP.
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llvm-svn: 55546
2008-08-29 18:29:46 +00:00
0673a8af14
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
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llvm-svn: 55545
2008-08-29 17:45:56 +00:00
b1a635b30c
regenerate
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llvm-svn: 55542
2008-08-29 17:20:18 +00:00
b25e5eab23
Asmprint nameless instructions as:
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%4 = add ...
instead of:
add ... ; 4
This makes opt -print-cfg output actually usable and makes .ll files
generally easier to read. This fixes PR2480
llvm-svn: 55541
2008-08-29 17:19:30 +00:00
a51c7030e2
Add support for parsing .ll files that have numbers in front of
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nameless values, such as:
%3 = add i32 4, 2
This fixes the first half of PR2480
llvm-svn: 55539
2008-08-29 17:12:13 +00:00
44b2138b9a
TableGen'ing instruction encodings.
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llvm-svn: 55533
2008-08-29 07:42:03 +00:00
c139c221dd
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
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llvm-svn: 55531
2008-08-29 07:40:52 +00:00
9f717afd68
MVN is addrmode1.
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llvm-svn: 55530
2008-08-29 07:36:24 +00:00
ee98fa9db2
More refactoring.
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llvm-svn: 55528
2008-08-29 06:41:12 +00:00
960b17a3c2
Swap fp comparison operands and change predicate to allow load folding.
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llvm-svn: 55521
2008-08-28 23:48:31 +00:00
2d37f19ef2
Refactor ARM instruction format definitions into a separate file. No functionality changes.
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llvm-svn: 55518
2008-08-28 23:39:26 +00:00
d58f3e36d0
Add a target callback for FastISel.
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llvm-svn: 55512
2008-08-28 23:21:34 +00:00
95d77f5466
remove tabs, fix > 80 cols
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llvm-svn: 55511
2008-08-28 23:19:51 +00:00
e6fe88391a
rename destroy -> releaseMemory to properly hook into passmgr.
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llvm-svn: 55508
2008-08-28 22:56:53 +00:00
b011a8f611
Add support for JIT exceptions on Darwin. Since we're dealing with libgcc,
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whose darwin code was written after the ability to dynamically register frames,
we need to do special hacks to make things work.
llvm-svn: 55507
2008-08-28 22:34:49 +00:00
f304a7aa4d
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
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llvm-svn: 55504
2008-08-28 21:40:38 +00:00
c45733f194
Implement null and undef values for FastISel.
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llvm-svn: 55500
2008-08-28 21:19:07 +00:00
1e137300bd
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
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llvm-svn: 55499
2008-08-28 21:04:05 +00:00
f27e33baa7
Optimize DAGCombiner's worklist processing. Previously it started
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its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.
This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.
llvm-svn: 55498
2008-08-28 21:01:56 +00:00
Evan Cheng