Commit Graph

81003 Commits

Author SHA1 Message Date
Diego Novillo b0257c8419 Tidy comment.
llvm-svn: 240987
2015-06-29 20:03:46 +00:00
Ben Langmuir 63aa8c5d28 Clean up unique lock files on signal and always release the lock
Make sure to remove the unique lock file, which is what the .lock
symlink points to, if there is a signal while the lock is held. This
will release the lock, since the symlink will point to nothing (already
tested in unit tests). For good measure, also clean up the unique lock
file if there is an error or signal before the lock is acquired.

I will add a clang test.

rdar://problem/21512307

llvm-svn: 240967
2015-06-29 17:08:41 +00:00
Alex Lorenz 8f6f4285f3 MIR Serialization: Serialize the register mask machine operands.
This commit implements serialization of the register mask machine
operands. This commit serializes only the call preserved register
masks that are defined by a target, it doesn't serialize arbitrary
register masks.

This commit also extends the TargetRegisterInfo class and TableGen so that
the users of TRI can get the list of all the call preserved register masks and
their names.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10673

llvm-svn: 240966
2015-06-29 16:57:06 +00:00
Benjamin Kramer 025f46f367 [SymbolSize] Skip sorting by index, just assign by index.
No functional change intended.

llvm-svn: 240961
2015-06-29 16:05:00 +00:00
Benjamin Kramer aa694a65a4 Upgrade JIT listeners for changes in the libObject API.
llvm-svn: 240956
2015-06-29 15:18:48 +00:00
Tobias Grosser 3cdc37c5bc Move delinearization from SCEVAddRecExpr to ScalarEvolution
The expressions we delinearize do not necessarily have to have a SCEVAddRecExpr
at the outermost level. At this moment, the additional flexibility  is not
exploited in LLVM itself, but in Polly we will soon soonish use this
functionality. For LLVM, this change should not affect existing functionality
(which is covered by test/Analysis/Delinearization/)

llvm-svn: 240952
2015-06-29 14:42:48 +00:00
Rafael Espindola 6a1bfb2f9b Factor out the checking of string tables.
This moves the error checking for string tables to getStringTable which returns
an ErrorOr<StringRef>.

This improves error checking, makes it uniform across all string tables and
makes it possible to check them once instead of once per name.

llvm-svn: 240950
2015-06-29 14:39:25 +00:00
Elena Demikhovsky 30bc4ca313 AVX-512: all forms of SCATTER instruction on SKX,
encoding, intrinsics and tests.

llvm-svn: 240936
2015-06-29 12:14:24 +00:00
Javed Absar 3f7c8934e4 [ARM]: Extend -mfpu options for half-precision and vfpv3xd
removing default label in switch as it results.
This is part of earlier commit http://reviews.llvm.org/D1064

Subscribers: llvm-commits
llvm-svn: 240932
2015-06-29 09:53:33 +00:00
Javed Absar d5526303b7 [ARM]: Extend -mfpu options for half-precision and vfpv3xd
Some of the the permissible ARM -mfpu options, which are supported in GCC,
are currently not present in llvm/clang.This patch adds the options:
'neon-fp16', 'vfpv3-fp16', 'vfpv3-d16-fp16', 'vfpv3xd' and 'vfpv3xd-fp16.
These are related to half-precision floating-point and single precision.

Reviewers: rengolin, ranjeet.singh

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10645

llvm-svn: 240930
2015-06-29 09:32:29 +00:00
Igor Breger a7a8e9a018 AVX-512: Implemented missing encoding and intrinsics for FMA instructions
Added tests for DAG lowering ,encoding and intrinsics

Differential Revision: http://reviews.llvm.org/D10796

llvm-svn: 240926
2015-06-29 09:10:00 +00:00
NAKAMURA Takumi 7bffb6954d Whitespace.
llvm-svn: 240924
2015-06-29 04:50:09 +00:00
Matt Arsenault 8ebce8f12b AMDGPU/SI: Fix extra space when printing v_div_fmas_*
llvm-svn: 240911
2015-06-28 18:16:14 +00:00
Jingyue Wu 3abde7bea5 [SLSR] S's basis must have the same type as S
llvm-svn: 240910
2015-06-28 17:45:05 +00:00
Asaf Badouh 7ec4b7a8bb [x86][AVX512]
Add vscalef support
include encoding and intrinsics


review:
http://reviews.llvm.org/D10730

llvm-svn: 240906
2015-06-28 14:30:39 +00:00
Elena Demikhovsky 6a1a357f1f AVX-512: Added all SKX forms of GATHER instructions.
Added intrinsics.
Added encoding and tests.

llvm-svn: 240905
2015-06-28 10:53:29 +00:00
Adrian Prantl cb53eedc79 Revert "Debug Info: One more bitfield bugfix. While yesterday's r240853 fixed"
This reverts commit 240890. Breaking the gdb buildbot.

llvm-svn: 240893
2015-06-27 21:55:00 +00:00
Benjamin Kramer 5b455f0b62 [SDAG] Now that we have a way to communicate the exact bit on sdiv use it to simplify sdiv by a constant.
We had a hack in SDAGBuilder in place to work around this but now we
can avoid that. Call BuildExactSDIV from BuildSDIV so DAGCombiner can
perform this trick automatically.

The added check in DAGCombiner is necessary to prevent exact sdiv by pow2
from regressing as the target-specific pow2 lowering is not aware of
exact bits yet.

This is mostly covered by existing tests. One side effect is that we
get the better lowering for exact vector sdivs now too :)

llvm-svn: 240891
2015-06-27 20:33:26 +00:00
Adrian Prantl 57c7a62b97 Debug Info: One more bitfield bugfix. While yesterday's r240853 fixed
the DW_AT_bit_offset computation, the byte offset is in fact also
endian-dependent as it needs to point to the storage unit containing the
most-significant bit of the the bitfield.
I'm so looking forward to emitting the endian-agnostic DWARF 3 version
instead.

llvm-svn: 240890
2015-06-27 20:12:43 +00:00
Daniel Sanders a3134fae17 [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.
Summary:
Previously it (incorrectly) used GPR's.

Patch by Simon Dardis. A couple small corrections by myself.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10567

llvm-svn: 240883
2015-06-27 15:39:19 +00:00
David Majnemer 9f3979fd78 [LoopVectorize] Pointer indicies may be wider than the pointer
If we are dealing with a pointer induction variable, isInductionPHI
gives back a step value of Stride / size of pointer.  However, we might
be indexing with a legal type wider than the pointer width.
Handle this by inserting casts where appropriate instead of crashing.

This fixes PR23954.

llvm-svn: 240877
2015-06-27 08:38:17 +00:00
David Majnemer 5185c3c271 [PruneEH] A naked, noinline function can return via InlineAsm
The PruneEH pass tries to annotate functions as 'noreturn' if it doesn't
see a ReturnInst.  However, a naked function containing inline assembly
can contain control flow leaving the function.

This fixes PR23971.

llvm-svn: 240876
2015-06-27 07:52:53 +00:00
Petr Hosek 3294670f6c [MC] Ensure that pending labels are flushed when -mc-relax-all flag is used
Summary:
The current implementation doesn't always flush all pending labels
beforeemitting data which can result in an incorrectly placed labels in
case when when instruction bundling is enabled and -mc-relax-all flag is
being used. To address this issue, we always flush pending labels before
emitting data.

The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.

Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063

Test Plan: Regression test attached

Reviewers: mseaborn

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10325

llvm-svn: 240870
2015-06-27 01:54:17 +00:00
Petr Hosek 4bbf563f6e [MC] Align fragments when -mc-relax-all flag is used
Summary:
Ensure that fragments are bundle aligned when instruction bundling
is enabled and the -mc-relax-all flag is set. This is implicitly
assumed by the bundle padding implementation but this assumption
does not hold when custom alignment is being used.

The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.

Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063

Test Plan: Regression test attached

Reviewers: mseaborn

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10044

llvm-svn: 240869
2015-06-27 01:49:53 +00:00
Duncan P. N. Exon Smith 1f8a99a9ae IR: Expose ModuleSlotTracker in Value::print()
Allow callers of `Value::print()` and `Metadata::print()` to pass in a
`ModuleSlotTracker`.  This allows them to pay only once for calculating
module-level slots (such as Metadata).

This is related to PR23865, where there was a huge cost for
`MachineFunction::print()`.  Although I don't have a *particular* user
in mind for this new code, I have hit big slowdowns before when running
`opt -debug`, and I think this will be useful.  Going forward, if
someone hits a big slowdown with `print()` statements, they can create a
`ModuleSlotTracker` and send it through.  Similarly, adding support to
`Value::dump()` and `Metadata::dump()` should be trivial.

I added unit tests to be sure the `print()` functions actually behave
the same way with and without the slot tracker.

llvm-svn: 240867
2015-06-27 00:38:26 +00:00
Peter Collingbourne ba4c8b5004 LowerBitSets: Ignore bitset entries that do not directly refer to a global.
It is possible for a global to be substituted with another global of a
different type or a different kind (i.e. an alias) at IR link time. One
example of this scenario is when a Microsoft ABI vtable is substituted with
an alias referring to a larger vtable containing an RTTI reference.

This will cause the global to be RAUW'd with a possibly bitcasted reference
to the other global. This will of course also affect any references to the
global in bitset metadata.

The right way to handle such metadata is simply to ignore it. This is sound
because the linked module should contain another copy of the bitset entries as
applied to the new global.

llvm-svn: 240866
2015-06-27 00:17:51 +00:00
Duncan P. N. Exon Smith f8b3ad611d Plug a leak introduced by r240848
Apparently this obvious leak was never exercised before, but r240848
exposed it.  Plug it.

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/5075

llvm-svn: 240865
2015-06-27 00:15:32 +00:00
Adrian Prantl d3da8caf67 Debug Info: Fix a bug in the DW_AT_bit_offset calculation that would
result in negative offsets and attempt a better job at documenting
the algorithm.

rdar://21082998

llvm-svn: 240853
2015-06-26 23:31:27 +00:00
Duncan P. N. Exon Smith c03745260e CodeGen: Create a proper ModuleSlotTracker for MachineInstr
Another follow-up related to r240848: try a little harder to share slot
tracking calculations within a single `MachineInstr` dump.  This is
unrelated to `MachineFunction::print()`, since that should be passing
through the function's `ModuleSlotTracker` by now, but could affect the
speed of dumping from a debugger if there is more than one IR-level
operand.

llvm-svn: 240852
2015-06-26 23:18:44 +00:00
Alex Lorenz 5d6108e4ed MIR Serialization: Serialize global address machine operands.
This commit serializes the global address machine operands.
This commit doesn't serialize the operand's offset and target
flags, it serializes only the global value reference.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10671

llvm-svn: 240851
2015-06-26 22:56:48 +00:00
Philip Reames 8fe7f13af8 [RewriteStatepointsForGC] Generalized vector phi/select handling for base pointers
This change extends the detection of base pointers for vector constructs to handle arbitrary phi and select nodes. The existing non-vector code already handles those, so this is basically just extending the vector special case to be less special cased. It still isn't generalized vector handling since we can't handle arbitrary vector instructions (e.g. shufflevectors), but it's a lot closer.

The general structure of the change is as follows:
 * Extend the base defining value relation over a subset of vector instructions and vector typed phi & select instructions.
 * Move scalarization from before base pointer rewriting to after base pointer rewriting. The extension of the BDV relation is sufficient to find vector base phis for vector inputs.
 * Preserve the existing special case logic for when the base of a vector element is locally obvious. This general idea could be extended to the scalar case as well.

Differential Revision: http://reviews.llvm.org/D10461#inline-84275

llvm-svn: 240850
2015-06-26 22:47:37 +00:00
Jingyue Wu 3203818bf7 [NVPTX] noop when kernel pointers are already global
Summary:
Some front ends make kernel pointers global already. In that case,
handlePointerParams does nothing.

Test Plan: more tests in lower-kernel-ptr-arg.ll

Reviewers: grosser

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10779

llvm-svn: 240849
2015-06-26 22:35:43 +00:00
Duncan P. N. Exon Smith 6529ed40bc CodeGen: Push the ModuleSlotTracker through Metadata
For another 1% speedup on the testcase in PR23865, push the
`ModuleSlotTracker` through to metadata-related printing in
`MachineBasicBlock::print()`.

llvm-svn: 240848
2015-06-26 22:28:47 +00:00
Philip Reames 007561acdc Minor style cleanup after 240843 [NFC]
Use a for-each loop in one case and rename the function to reflect it's new usage.

llvm-svn: 240847
2015-06-26 22:21:52 +00:00
Duncan P. N. Exon Smith f48e982706 CodeGen: Push the ModuleSlotTracker through MachineOperands
Push `ModuleSlotTracker` through `MachineOperand`s, dropping the time
for `llc -print-machineinstrs` on the testcase in PR23865 from ~13
seconds to ~9 seconds.  Now `SlotTracker::processFunctionMetadata()`
accounts for only 8% of the runtime, which seems reasonable.

llvm-svn: 240845
2015-06-26 22:06:47 +00:00
Philip Reames 9818dd77b4 [Verifier] Follow on to 240836
Address one missed review comment and do the rename I left out of that patch to make it reviewable.

llvm-svn: 240843
2015-06-26 22:04:34 +00:00
Duncan P. N. Exon Smith 3269215401 CodeGen: Use a single SlotTracker in MachineFunction::print()
Expose enough of the IR-level `SlotTracker` so that
`MachineFunction::print()` can use a single one for printing
`BasicBlock`s.  Next step would be to lift this through a few more APIs
so that we can make other print methods faster.

Fixes PR23865, changing the runtime of `llc -print-machineinstrs` from
many minutes (killed after 3 minutes, but it wasn't very close) to
13 seconds for a 502185 line dump.

llvm-svn: 240842
2015-06-26 22:04:20 +00:00
Tom Stellard 4694ed0a14 AMDPGU/SI: Use correct resource descriptors for VI on HSA
Summary: We need to set MTYPE = 2 for VI shaders when targeting the HSA runtime.

Reviewers: arsenm

Differential Revision: http://reviews.llvm.org/D10777

llvm-svn: 240841
2015-06-26 21:58:42 +00:00
Tom Stellard ff7416ba06 AMDGPU/SI: Update amd_kernel_code_t definition and add assembler support
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10772

llvm-svn: 240839
2015-06-26 21:58:31 +00:00
Tom Stellard 833ae4fadd AMDGPU/SI: Remove unused variable
This should fix some bots that were broken by r240831.

llvm-svn: 240838
2015-06-26 21:58:26 +00:00
Philip Reames a3c6f0048c [Verifier] Verify invokes of intrinsics
We support invoking a subset of llvm's intrinsics, but the verifier didn't account for this.  We had previously added a special case to verify invokes of statepoints.  By generalizing the code in terms of CallSite, we can verify invokes of other intrinsics as well.  Interestingly, this found one test case which was invalid.

Note: I'm deliberately leaving the naming change from CI to CS to a follow up change.  That will happen shortly, I just wanted to reduce the diff to make it clear what was happening with this one.

Differential Revision: http://reviews.llvm.org/D10118

llvm-svn: 240836
2015-06-26 21:39:44 +00:00
Adrian Prantl 06b298e4b6 Debug Info: Clarify the documentation for bitfields emission.
llvm-svn: 240835
2015-06-26 21:27:30 +00:00
Tom Stellard 91efe9cebe AMDGPU/SI: Set ELF OS/ABI to ELFOSABI_AMDGPU_HSA
Reviewers: arsenm, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10708

llvm-svn: 240832
2015-06-26 21:15:11 +00:00
Tom Stellard 347ac79b15 AMDGPU/SI: Add hsa code object directives
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10757

llvm-svn: 240831
2015-06-26 21:15:07 +00:00
Tom Stellard b5798b09d3 AMDGPU/SI: There are no implicit kernel args in the amdhsa ABI
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10706

llvm-svn: 240830
2015-06-26 21:15:03 +00:00
Tom Stellard f151a45ccd AMDGPU/SI: Emit amd_kernel_code_t in EmitFunctionBodyStart()
Summary:
This way the function symbol points to the start of amd_kernel_code_t
rather than the start of the function.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10705

llvm-svn: 240829
2015-06-26 21:14:58 +00:00
Philip Reames 9b5c9580e3 Teach InlineCost to account for a null check which can be folded away
If we have a caller that knows a particular argument can never be null, we can exploit this fact while simplifying values in the inline cost analysis. This has the effect of reducing the cost for inlining when a null check is present in the callee, but the value is known non null in the caller. In particular, any dependent control flow can be discounted from the cost estimate.

Note that we use the parameter attributes at the call site to memoize the analysis within the caller's code.  The setting of this attribute is done in InstCombine, the inline cost analysis just consumes it.  This is intentional and important because we want the inline cost analysis results to be easily cachable themselves.  We're not currently doing so, but initial results on LTO indicate this will quickly become important.

Differential Revision: http://reviews.llvm.org/D9129

llvm-svn: 240828
2015-06-26 20:51:17 +00:00
Marek Olsak cfbdba2d0b AMDGPU: really don't commute REV opcodes if the target variant doesn't exist
If pseudoToMCOpcode failed, we would return the original opcode, so operands
would be swapped, but the instruction would remain the same.
It resulted in LSHLREV a, b ---> LSHLREV b, a.

This fixes Glamor text rendering and
piglit/arb_sample_shading-builtin-gl-sample-mask on VI.

This is a candidate for stable branches.

v2: the test was simplified by Tom Stellard
llvm-svn: 240824
2015-06-26 20:29:10 +00:00
Pete Cooper 485d1146db Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.

llvm-svn: 240822
2015-06-26 19:37:02 +00:00
Nemanja Ivanovic f502a428e6 Add missing builtins to the PPC back end for ABI compliance (vol. 1)
This patch corresponds to review:
http://reviews.llvm.org/D10638

This is the back end portion of patch
http://reviews.llvm.org/D10637
It just adds the code gen and intrinsic functions necessary to support that patch to the back end.

llvm-svn: 240820
2015-06-26 19:26:53 +00:00
Pete Cooper af61ac71e2 Wrap assert loops in #ifndef NDEBUG
The body of the loops here only contained asserts.  This triggered an unused variable
warning on release builds and -Werror on the bots.

llvm-svn: 240819
2015-06-26 19:23:20 +00:00
Pete Cooper 9271ccc345 Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.

llvm-svn: 240817
2015-06-26 19:18:49 +00:00
Pete Cooper 8fc121dfc4 Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.

llvm-svn: 240815
2015-06-26 19:08:33 +00:00
Matt Arsenault 572c29afc9 Show invariant loads in MMO dumping
llvm-svn: 240813
2015-06-26 19:00:11 +00:00
David Majnemer 65ff7ccf21 Revert "Revert r240762 "[X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstant""
This reverts commit r240793 while fixing how we handle array constant
pool entries.

This fixes PR23966.

llvm-svn: 240811
2015-06-26 18:55:48 +00:00
Pete Cooper 8c0a710995 Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.

llvm-svn: 240809
2015-06-26 18:41:54 +00:00
Pete Cooper 3af9a25b65 Add op_values() to iterate over the SDValue operands of an SDNode.
SDNode already had ops() which would iterate over the operands and return
SDUse*.  This version instead gets the SDValue's out of the SDUse's so that
we can use foreach in more places.

Reviewed by David Blaikie.

llvm-svn: 240805
2015-06-26 18:17:36 +00:00
David Blaikie b447ac6435 Move VectorUtils from Transforms to Analysis to correct layering violation
llvm-svn: 240804
2015-06-26 18:02:52 +00:00
Javed Absar bced3032e0 [ARM] Cortex-R5 is not VFPOnlySP
This patch fixes the error in ARM.td which stated that Cortex-R5
floating point unit can do only single precision, when it can do double as well.

Reviewers: rengolin

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10769

llvm-svn: 240799
2015-06-26 17:42:37 +00:00
Adam Nemet c4866d29dd [LAA] Try to prove non-wrapping of pointers if SCEV cannot
Summary:
Scalar evolution does not propagate the non-wrapping flags to values
that are derived from a non-wrapping induction variable because
the non-wrapping property could be flow-sensitive.

This change is a first attempt to establish the non-wrapping property in
some simple cases.  The main idea is to look through the operations
defining the pointer.  As long as we arrive to a non-wrapping AddRec via
a small chain of non-wrapping instruction, the pointer should not wrap
either.

I believe that this essentially is what Andy described in
http://article.gmane.org/gmane.comp.compilers.llvm.cvs/220731 as the way
forward.

Reviewers: aschwaighofer, nadav, sanjoy, atrick

Reviewed By: atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10472

llvm-svn: 240798
2015-06-26 17:25:43 +00:00
Alex Lorenz ec6b26b955 Fix unused variable from r240792.
The variable 'I' wasn't used when assertions were disabled.
This commit ensures that 'I' is used outside of an assert.

llvm-svn: 240797
2015-06-26 17:07:27 +00:00
Benjamin Kramer 1dcd8b09b4 [DAGCombine] Fix demanded bits computation for exact shifts.
Fixes a miscompilation of MultiSource/Benchmarks/MallocBench/gs

llvm-svn: 240796
2015-06-26 16:59:31 +00:00
Douglas Katzman 289ec857d2 [X86]: Correctly sign-extend 16-bit immediate in CALL instruction.
Patch by Matthew Barney. Thanks!

Differential Revision: http://reviews.llvm.org/D9514

llvm-svn: 240795
2015-06-26 16:58:59 +00:00
David Blaikie 1213dbf1fd Fix ODR violation waiting to happen by making static function definitions in VectorUtils.h non-static and defined out of line
Patch by Ashutosh Nema

Differential Revision: http://reviews.llvm.org/D10682

llvm-svn: 240794
2015-06-26 16:57:30 +00:00
Hans Wennborg e38fc05d3b Revert r240762 "[X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstant"
It seems to have caused PR23966: "UNREACHABLE executed at ..\lib\Target\X86\X86TargetObjectFile.cpp:148"

llvm-svn: 240793
2015-06-26 16:48:02 +00:00
Alex Lorenz 33f0aef32f MIR Serialization: Serialize machine basic block operands.
This commit serializes machine basic block operands. The
machine basic block operands use the following syntax:

  %bb.<id>[.<name>]

This commit also modifies the YAML representation for the
machine basic blocks - a new, required field 'id' is added
to the MBB YAML mapping.

The id is used to resolve the MBB references to the
actual MBBs. And while the name of the MBB can be
included in a MBB reference, this name isn't used to
resolve MBB references - as it's possible that multiple
MBBs will reference the same BB and thus they will have the
same name. If the name is specified, the parser will verify
that it is equal to the name of the MBB with the specified id.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10608

llvm-svn: 240792
2015-06-26 16:46:11 +00:00
Benjamin Kramer c2ae767377 [DAGCombiner] Preserve the exact bit when simplifying SRA to SRL.
Allows more aggressive folding of ashr/shl pairs.

llvm-svn: 240788
2015-06-26 14:51:49 +00:00
Benjamin Kramer 07e70b4fa4 [DAGCombine] fold (X >>?,exact C1) << C2 --> X << (C2-C1)
Instcombine also does this but many opportunities only become visible
after GEPs are lowered.

llvm-svn: 240787
2015-06-26 14:51:36 +00:00
Rafael Espindola 854038ed1a Rename getObjectFile to getObject for consistency.
llvm-svn: 240785
2015-06-26 14:51:16 +00:00
Toma Tabacu 0a6fa59a2c [mips] [IAS] Add partial support for the ULW pseudo-instruction.
Summary:
This only adds support for ULW of an immediate address with/without a source register.
It does not include support for ULW of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9663

llvm-svn: 240782
2015-06-26 13:20:17 +00:00
Rafael Espindola edd5f84419 Expose getFlags via ELFSectionRef.
llvm-svn: 240779
2015-06-26 12:44:10 +00:00
Rafael Espindola 41401e9c80 Add a ELFSectionRef class and use it to expose getSectionType.
llvm-svn: 240778
2015-06-26 12:33:37 +00:00
Rafael Espindola 2fa80cc5fd Simplify getSymbolType.
This is still a really odd function. Most calls are in object format specific
contexts and should probably be replaced with a more direct query, but at least
now this is not too obnoxious to use.

llvm-svn: 240777
2015-06-26 12:18:49 +00:00
Javed Absar 99a9343ae6 [ARM] Cortex-R4F is not VFPOnlySP
Cortex-R4F TRM states that fpu supports both single and double precision.
This patch corrects the information in ARM.td file and corresponding test.

Reviewers: rengolin

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10763

llvm-svn: 240776
2015-06-26 12:14:56 +00:00
Rafael Espindola eef7ffe2e9 Make getOther ELF only.
No other format has this field.

llvm-svn: 240774
2015-06-26 11:39:57 +00:00
Rafael Espindola c5fb508c9d Optimize the creation of mapping symbols.
No need to create two symbols just to assign one to the other.

llvm-svn: 240773
2015-06-26 11:31:13 +00:00
David Majnemer 4eb32e7d21 [X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstant
No functionality changed, just keeping things clean.

llvm-svn: 240762
2015-06-26 07:03:12 +00:00
Hao Liu b41c0b44af [InterleavedAccess] Fix failures "undefined type 'llvm::raw_ostream'" on windows.
llvm-svn: 240760
2015-06-26 04:38:21 +00:00
Hao Liu 2cd34bb585 [ARM] Lower interleaved memory accesses to vldN/vstN intrinsics.
This patch also adds a function to calculate the cost of interleaved memory accesses.

E.g. Lower an interleaved load:
        %wide.vec = load <8 x i32>, <8 x i32>* %ptr, align 4
        %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>
        %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>
     into:
        %vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(%ptr, 4)
        %vec0 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 0
        %vec1 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 1

E.g. Lower an interleaved store:
        %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
        store <12 x i32> %i.vec, <12 x i32>* %ptr, align 4
     into:
        %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
        %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
        %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
        call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4)

Differential Revision: http://reviews.llvm.org/D10533

llvm-svn: 240755
2015-06-26 02:45:36 +00:00
Hao Liu 7ec8ee3119 [AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch also adds a function to calculate the cost of interleaved memory accesses.
E.g. Lower an interleaved load:
        %wide.vec = load <8 x i32>, <8 x i32>* %ptr
        %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>
        %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>
     into:
        %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
        %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
        %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1

E.g. Lower an interleaved store:
        %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
        store <12 x i32> %i.vec, <12 x i32>* %ptr
     into:
        %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
        %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
        %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
        call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)

Differential Revision: http://reviews.llvm.org/D10533

llvm-svn: 240754
2015-06-26 02:32:07 +00:00
Hao Liu 1c1e0c9e71 [InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory accesses and transform into target specific intrinsics.
E.g. An interleaved load (Factor = 2):
        %wide.vec = load <8 x i32>, <8 x i32>* %ptr
        %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
        %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend.

E.g. An interleaved store (Factor = 3):
        %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
        store <12 x i32> %i.vec, <12 x i32>* %ptr
It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend.

Differential Revision: http://reviews.llvm.org/D10533

llvm-svn: 240751
2015-06-26 02:10:27 +00:00
Matthias Braun 7c6d6491dd Revert "X86: Reject register operands with obvious type mismatches."
Revert until http://llvm.org/PR23955 is investigated.

This reverts commit r239309.

llvm-svn: 240746
2015-06-26 00:26:49 +00:00
Alexey Samsonov 773e8c3966 [ASan] Use llvm::getDISubprogram() to get function entry debug location.
It can be more robust than copying debug info from first non-alloca
instruction in the entry basic block. We use the same strategy in
coverage instrumentation.

llvm-svn: 240738
2015-06-26 00:00:47 +00:00
Duncan P. N. Exon Smith 827200c822 AsmPrinter: Use an intrusively linked list for DIE::Children
Replace the `std::vector<>` for `DIE::Children` with an intrusively
linked list.  This is a strict memory improvement: it requires no
auxiliary storage, and reduces `sizeof(DIE)` by one pointer.  It also
factors out the DIE-related malloc traffic.

This drops llc memory usage from 735 MB down to 718 MB, or ~2.3%.

(I'm looking at `llc` memory usage on `verify-uselistorder.lto.opt.bc`;
see r236629 for details.)

llvm-svn: 240736
2015-06-25 23:52:10 +00:00
Duncan P. N. Exon Smith 4fb1f9cda6 AsmPrinter: Convert DIE::Values to a linked list
Change `DIE::Values` to a singly linked list, where each node is
allocated on a `BumpPtrAllocator`.  In order to support `push_back()`,
the list is circular, and points at the tail element instead of the
head.  I abstracted the core list logic out to `IntrusiveBackList` so
that it can be reused for `DIE::Children`, which also cares about
`push_back()`.

This drops llc memory usage from 799 MB down to 735 MB, about 8%.

(I'm looking at `llc` memory usage on `verify-uselistorder.lto.opt.bc`;
see r236629 for details.)

llvm-svn: 240733
2015-06-25 23:46:41 +00:00
NAKAMURA Takumi 520b45df84 PPCISelLowering.cpp: Appease PR23956. [-Wdocumentation]
llvm-svn: 240727
2015-06-25 23:38:44 +00:00
Anna Zaks 785c075786 [asan] Do not instrument special purpose LLVM sections.
Do not instrument globals that are placed in sections containing "__llvm"
in their name.

This fixes a bug in ASan / PGO interoperability. ASan interferes with LLVM's
PGO, which places its globals into a special section, which is memcpy-ed by
the linker as a whole. When those goals are instrumented, ASan's memcpy wrapper
reports an issue.

http://reviews.llvm.org/D10541

llvm-svn: 240723
2015-06-25 23:35:48 +00:00
Anna Zaks 4f652b69b1 [asan] Don't run stack malloc on functions containing inline assembly.
It makes LLVM run out of registers even on 64-bit platforms. For example, the
following test case fails on darwin.

clang -cc1 -O0 -triple x86_64-apple-macosx10.10.0 -emit-obj -fsanitize=address -mstackrealign -o ~/tmp/ex.o -x c ex.c
error: inline assembly requires more registers than available

void TestInlineAssembly(const unsigned char *S, unsigned int pS, unsigned char *D, unsigned int pD, unsigned int h) {

unsigned int sr = 4, pDiffD = pD - 5;
unsigned int pDiffS = (pS << 1) - 5;
char flagSA = ((pS & 15) == 0),
flagDA = ((pD & 15) == 0);
asm volatile (
  "mov %0,  %%"PTR_REG("si")"\n"
  "mov %2,  %%"PTR_REG("cx")"\n"
  "mov %1,  %%"PTR_REG("di")"\n"
  "mov %8,  %%"PTR_REG("ax")"\n"
  :
  : "m" (S), "m" (D), "m" (pS), "m" (pDiffS), "m" (pDiffD), "m" (sr), "m" (flagSA), "m" (flagDA), "m" (h)
  : "%"PTR_REG("si"), "%"PTR_REG("di"), "%"PTR_REG("ax"), "%"PTR_REG("cx"), "%"PTR_REG("dx"), "memory"
);
}

http://reviews.llvm.org/D10719

llvm-svn: 240722
2015-06-25 23:35:45 +00:00
Matt Arsenault f735cab986 DAGCombiner: Use pop_back_val()
llvm-svn: 240709
2015-06-25 22:15:05 +00:00
Rafael Espindola dbb6bd3345 Add an ELFSymbolRef type.
This allows user code to say Sym.getSize() instead of having to manually fetch
the object.

llvm-svn: 240708
2015-06-25 22:10:04 +00:00
Frederic Riss 16238d90b2 IAS: Use the root macro instanciation for location
r224810 fixed the handling of macro debug locations in AsmParser. This patch
fixes the logic to actually do what was intended: it uses the first macro of
the macro stack instead of the last one. The updated testcase shows that the
current scheme doesn't work when macro instanciations are nested and multiple
files are used.

Reviewers: compnerd

Differential Revision: http://reviews.llvm.org/D10463

llvm-svn: 240705
2015-06-25 21:57:33 +00:00
Sanjay Patel e4aedb55d6 fix typos; NFC
llvm-svn: 240699
2015-06-25 21:11:08 +00:00
Pete Cooper 125ad17fed Use foreach loop over constant operands. NFC.
A number of places had explicit loops over Constant::operands().
Just use foreach loops where possible.

llvm-svn: 240694
2015-06-25 20:51:38 +00:00
Jingyue Wu 5e34ce33f5 [InstCombine] call SimplifyICmpInst with correct context
Summary:
Fixes PR23809. Without passing the context to SimplifyICmpInst, we would
use the assume to prove that the condition feeding the assume is
trivially true (see isValidAssumeForContext in ValueTracking.cpp),
causing the removal of the assume which may be useful for later
optimizations.

Test Plan: pr23800.ll

Reviewers: hfinkel, majnemer

Reviewed By: hfinkel

Subscribers: henryhu, llvm-commits, wengxt, broune, meheff, eliben

Differential Revision: http://reviews.llvm.org/D10695

llvm-svn: 240683
2015-06-25 20:14:47 +00:00
Rafael Espindola 6dff814cdf Diagnose undefined temporary symbols.
We already disallowed

.global .Lfoo

so this is reasonable.

This is a small cherry pick from r240130.

llvm-svn: 240681
2015-06-25 20:10:45 +00:00
Yaron Keren 62064d6d38 Rangify for loop in Inliner.cpp. NFC.
llvm-svn: 240678
2015-06-25 19:28:24 +00:00
Matt Arsenault c244dcb804 DAGCombiner: Remove redundant check
MemIntrinsicSDNode is already a subclass of MemSDNode,
so the MemSDNode check is sufficient.

llvm-svn: 240672
2015-06-25 18:47:02 +00:00
Peter Collingbourne 2a3443c7c5 GVN: If a branch has two identical successors, we cannot declare either dead.
This previously caused miscompilations as a result of phi nodes receiving
undef incoming values from blocks dominated by such successors.

Differential Revision: http://reviews.llvm.org/D10726

llvm-svn: 240670
2015-06-25 18:32:02 +00:00
Kit Barton 13894c7f35 [PPC] Implement vmrgew and vmrgow instructions
This patch adds support for the vector merge even word and vector merge odd word
instructions introduced in POWER8.

Phabricator review: http://reviews.llvm.org/D10704

llvm-svn: 240650
2015-06-25 15:17:40 +00:00
Bruno Cardoso Lopes edb876d52c [AsmPrinter] Fix crash in handleIndirectSymViaGOTPCRel
Check for symbols in MCValue before using them. Bail out early in case
they are null. This fixes PR23779.

Differential Revision: http://reviews.llvm.org/D10712

rdar://problem/21532830

llvm-svn: 240649
2015-06-25 15:17:23 +00:00
Rafael Espindola d8e96ec79c Use computeSymbolSizes in llvm-symbolize.
llvm-svn: 240646
2015-06-25 15:06:38 +00:00
Benjamin Kramer 92861d7449 [PPC] Replace debug value skipping with getLastNonDebugInstr.
No functionality change intended.

llvm-svn: 240641
2015-06-25 13:39:03 +00:00
Benjamin Kramer e61cbd1f3a Replace copy-pasted debug value skipping with MBB::getLastNonDebugInstr
No functional change intended.

llvm-svn: 240639
2015-06-25 13:28:24 +00:00
Toma Tabacu a64e540511 [mips] [IAS] Refactor the emitDirectiveModuleFP() functions. NFC.
Summary:
Simplify emitDirectiveModuleFP() by having it just print the current information
from MipsABIFlagsSection and doing an updateABIInfo() before such calls.

This prevents us from forgetting to update the STI.FeatureBits,
because updateABIInfo() uses those to update the MipsABIFlagsSection object,
and also makes sure we use the update mechanism from MipsABIFlagsSection.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits, mpf

Differential Revision: http://reviews.llvm.org/D10642

llvm-svn: 240637
2015-06-25 12:44:38 +00:00
Artur Pilipenko 0e21d54b51 Take alignment into account in isSafeToLoadUnconditionally
Reviewed By: hfinkel

Differential Revision: http://reviews.llvm.org/D10475

llvm-svn: 240636
2015-06-25 12:18:43 +00:00
Ulrich Weigand 77884bcb5d [SystemZ] Only attempt RxSBG optimization for integer types
As pointed out by Justin Bogner (see r240520), SystemZDAGToDAGISel::Select
currently attempts to convert boolean operations into RxSBG even on some
non-integer types (in particular, vector types).  This would not work in
any case, and it happened to trigger undefined behaviour in allOnes.

This patch verifies that we have a (<= 64-bit) integer type before
attempting to perform this optimization.

llvm-svn: 240634
2015-06-25 11:52:36 +00:00
Toma Tabacu 3c49958945 [mips] [IAS] Refactor the emitDirectiveModuleOddSPReg() functions. NFC.
Summary:
We can simplify emitDirectiveModuleOddSPReg() by having it print the current OddSPReg information
from MipsABIFlagsSection and doing an updateABIInfo() before such calls.

This prevents us from forgetting to update the STI.FeatureBits, because updateABIInfo() uses those to update the MipsABIFlagsSection object,
and also makes sure we use the update mechanism from MipsABIFlagsSection.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits, mpf

Differential Revision: http://reviews.llvm.org/D10641

llvm-svn: 240630
2015-06-25 10:56:57 +00:00
Jay Foad 7a28cdc9dd Teach LLVM about the PPC64 memory sanitizer implementation.
Summary:
This is the LLVM part of the PPC memory sanitizer implementation in
D10648.

Reviewers: kcc, samsonov, willschm, wschmidt, eugenis

Reviewed By: eugenis

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10649

llvm-svn: 240627
2015-06-25 10:34:29 +00:00
Toma Tabacu 7bc44dcb0c [mips] [IAS] Fix parsing of memory offset expressions with parenthesis depth >1.
Summary:
In an expression such as "(((a+b)+c)+d)", parseParenExpression() would only parse the "a+b)+c", which would result in an error later on in the parser.
This means that we can only parse one level of inner parentheses.

In order to fix this, I added a new function called parseParenExprOfDepth(), which parses a specified number of trailing parenthesis expressions
(except for the outermost parenthesis), and changed MipsAsmParser to use it in parseMemOffset instead of parseParenExpression().

Reviewers: dsanders, rafael

Reviewed By: dsanders, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9742

llvm-svn: 240625
2015-06-25 09:52:02 +00:00
Ahmed Bougacha f1eccbecf8 [X86] Accept hasAVX512() as well as hasFMA() when generating FMA.
We don't always have FMA, for example when using 'clang -mavx512f'
without an explicit CPU.

Also check for an explicit +avx512f instead of CPUs in a couple
related tests.

llvm-svn: 240616
2015-06-25 00:44:46 +00:00
Swaroop Sridhar e9247ab6d6 Enable StackMap Serialization for COFF
Summary

This change turns on the emission of 
__LLVM_Stackmaps section when generating COFF binaries.

Test Plan

Added a scenario to the test case: 
test\CodeGen\X86\statepoint-stackmap-format.ll.

Code Review:

http://reviews.llvm.org/D10680

llvm-svn: 240613
2015-06-25 00:28:42 +00:00
Rui Ueyama 6a75acb1c2 libObject/COFF: Add a function to get pointers to relocation entries.
llvm-svn: 240610
2015-06-25 00:07:39 +00:00
Duncan P. N. Exon Smith 817ac8f40a Add simplify_type<const WeakVH>; simplify IndVarSimplify
r240214 fixed some UB in IndVarSimplify, and it needed a temporary
`WeakVH` to do it.  Add `simplify_type<const WeakVH>` so that this
temporary isn't necessary.

llvm-svn: 240599
2015-06-24 22:23:21 +00:00
Douglas Katzman fcda6f8c6b [X86] Simplify some stuff in X86DisassemblerDecoder. NFC
- Deciding that insn->sibIndex is SIB_INDEX_NONE does not require another
check beyond the fully decoded bits being equal to 0x4.
The expression insn->sibIndex == SIB_INDEX_sib could not have been true unless
index were 0x4, because SIB_INDEX_sib is merely the range base (SIB_INDEX_EAX)
plus 4. Respectively SIB_INDEX_sib64.

- Don't use a switch statement to perform left-shift.

Differential Revision: http://reviews.llvm.org/D9762

llvm-svn: 240598
2015-06-24 22:04:55 +00:00
David Majnemer 63d606bdcb [GVN] Intersect the IR flags when CSE'ing two instructions
We performed a simple, but incomplete, intersection when it came time to
CSE instructions.  It didn't handle, for example, the 'exact' flag.

This fixes PR23922.

llvm-svn: 240595
2015-06-24 21:52:25 +00:00
David Majnemer f6e500a0dc [Reassociate] Don't propogate flags when creating negations
Reassociate mutated existing instructions in order to form negations
which would create additional reassociate opportunities.

This fixes PR23926.

llvm-svn: 240593
2015-06-24 21:27:36 +00:00
Sanjay Patel 64ea207027 fix typos; NFC
llvm-svn: 240592
2015-06-24 20:42:33 +00:00
Sanjay Patel 09159b8f47 don't repeat function names in comments; NFC
llvm-svn: 240591
2015-06-24 20:40:57 +00:00
Akira Hatanaka 14348aa2c5 [If Converter] Convert recursion to iteration.
This commit makes changes to IfConverter::AnalyzeBlock to use iteration instead
of recursion. Previously, this function would get called recursively a large
number of times and eventually segfault when a function with the following CFG
was compiled:

BB0:
 if (condition0)
  goto BB1
 goto BB2
BB1:
 goto BB2
BB2:
 if (condition1)
  goto BB3
 goto BB4
BB3:
...
(repeat until BB7488)

rdar://problem/21386145

Differential Revision: http://reviews.llvm.org/D10587

llvm-svn: 240589
2015-06-24 20:34:35 +00:00
Pete Cooper 75403d7753 Devirtualize Instruction::clone_impl
llvm-svn: 240588
2015-06-24 20:22:23 +00:00
Jingyue Wu 9c71150bfb Add NVPTXPeephole pass to reduce unnecessary address cast
Summary:
This patch first change the register that holds local address for stack
frame to %SPL. Then the new NVPTXPeephole pass will try to scan the
following pattern

   %vreg0<def> = LEA_ADDRi64 <fi#0>, 4
   %vreg1<def> = cvta_to_local %vreg0

and transform it into

   %vreg1<def> = LEA_ADDRi64 %VRFrameLocal, 4

Patched by Xuetian Weng

Test Plan: test/CodeGen/NVPTX/local-stack-frame.ll

Reviewers: jholewinski, jingyue

Reviewed By: jingyue

Subscribers: eliben, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10549

llvm-svn: 240587
2015-06-24 20:20:16 +00:00
Sanjay Patel adb110c372 fix typos; NFC
llvm-svn: 240585
2015-06-24 20:07:50 +00:00
Matthias Braun ba3ecc3c80 ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually test for it
This fixes PR23912

Differential Revision: http://reviews.llvm.org/D10620

llvm-svn: 240582
2015-06-24 20:03:27 +00:00
Rafael Espindola 6bf322101b Make computeSymbolSizes never fail.
On ELF that was already the case since getting the size of a symbol
never fails.

On MachO and COFF we could fail trying to get the section of a symbol. But
we don't really need the section, just the section number to know if two
symbols are in the same section or not.

llvm-svn: 240580
2015-06-24 19:57:32 +00:00
Alex Lorenz 54565cf02b MIR Serialization: Serialize simple MachineRegisterInfo attributes.
This commit serializes the 3 scalar boolean attributes from the
MachineRegisterInfo class: IsSSA, TracksRegLiveness, and
TracksSubRegLiveness. These attributes are serialized as part
of the machine function YAML mapping.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10618

llvm-svn: 240579
2015-06-24 19:56:10 +00:00
Rafael Espindola 7308d290bf Use Symbol::getValue to simplify object::computeSymbolSizes. NFC.
llvm-svn: 240575
2015-06-24 19:32:52 +00:00
Jingyue Wu 6f72aed3ec [LSR] canonicalize Prod*(1<<C) to Prod<<C
Summary:
Because LSR happens at a late stage where mul of a power of 2 is
typically canonicalized to shl, this canonicalization emits code that
can be better CSE'ed.

Test Plan:
Transforms/LoopStrengthReduce/shl.ll shows how this change makes GVN more
powerful. Fixes some existing tests due to this change.

Reviewers: sanjoy, majnemer, atrick

Reviewed By: majnemer, atrick

Subscribers: majnemer, llvm-commits

Differential Revision: http://reviews.llvm.org/D10448

llvm-svn: 240573
2015-06-24 19:28:40 +00:00
Rafael Espindola c1ffd69c34 Use Symbol.getValue to simplify RuntimeDyldCOFF::getSymbolOffset. NFC.
llvm-svn: 240572
2015-06-24 19:27:53 +00:00
Rafael Espindola 991af666f1 Add a SymbolRef::getValue.
This returns either the symbol offset or address. Since it is not defined which
one, it never has to lookup the section and so never fails.

I will add users in the next commit.

llvm-svn: 240569
2015-06-24 19:11:10 +00:00
Pete Cooper 5815b1fd56 Devirtualize Constant::replaceUsesOfWithOnConstant.
This is part of the work to devirtualize Value.

The old pattern was to call replaceUsesOfWithOnConstant which was overridden by
subclasses.  Those could then call replaceUsesOfWithOnConstantImpl on Constant
to handle deleting the current value.

To be consistent with other parts of the code, this has been changed so that we
call the method on Constant, and that dispatches to an Impl on subclasses.

As part of this, it made sense to rename the methods to be more descriptive.  The
new name is Constant::handleOperandChange, and it requires that all subclasses of
Constant implement handleOperandChangeImpl, even if they just throw an error if
they shouldn't be called.

Reviewed by Duncan Exon Smith.

llvm-svn: 240567
2015-06-24 18:55:24 +00:00
Duncan P. N. Exon Smith 9dbb5013b7 AsmPrinter: Cleanup DIEValue::EmitValue() API, NFC
Stop taking a `dwarf::Form` in `DIEValue::EmitValue()` and
`DIEValue::SizeOf()`, since they're always passed `DIEValue::getForm()`
anyway.  This is just left over from when `DIEValue` didn't know its own
form.

llvm-svn: 240566
2015-06-24 18:48:11 +00:00
Rafael Espindola 59128921f6 Refactor duplicated code. NFC.
llvm-svn: 240563
2015-06-24 18:14:41 +00:00
Bruno Cardoso Lopes 7900ef891f [CaptureTracking] Avoid long compilation time on large basic blocks
CaptureTracking becomes very expensive in large basic blocks while
calling PointerMayBeCaptured. PointerMayBeCaptured scans the BB the
number of times equal to the number of uses of 'BeforeHere', which is
currently capped at 20 and bails out with Tracker->tooManyUses().

The bottleneck here is the number of calls to PointerMayBeCaptured * the
basic block scan. In a testcase with a 82k instruction BB,
PointerMayBeCaptured is called 130k times, leading to 'shouldExplore'
taking 527k runs, this currently takes ~12min.

To fix this we locally (within PointerMayBeCaptured) number the
instructions in the basic block using a DenseMap to cache instruction
positions/numbers. We build the cache incrementally every time we need
to scan an unexplored part of the BB, improving compile time to only
take ~2min.

This triggers in the flow: DeadStoreElimination -> MepDepAnalysis ->
CaptureTracking.

Side note: after multiple runs in the test-suite I've seen no
performance nor compile time regressions, but could note a couple of
compile time improvements:

Performance Improvements - Compile Time Delta Previous  Current StdDev
SingleSource/Benchmarks/Misc-C++/bigfib -4.48%  0.8547  0.8164  0.0022
MultiSource/Benchmarks/TSVC/LoopRerolling-dbl/LoopRerolling-dbl -1.47% 1.3912  1.3707  0.0056

Differential Revision: http://reviews.llvm.org/D7010

llvm-svn: 240560
2015-06-24 17:53:17 +00:00
Alex Lorenz 12b554e6a7 MIR Serialization: Serialize the null register operands.
This commit serializes the null register machine operands.
It uses the '_' keyword to represent them, but the parser
also allows the '%noreg' named register syntax.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10580

llvm-svn: 240558
2015-06-24 17:34:58 +00:00
Michael Zolotukhin 79ff564ef3 [LoopVectorizer] Fix bailing-out condition for OptForSize case.
With option OptForSize enabled, the Loop Vectorizer is not supposed to
create tail loop. The condition checking that was invalid and was not
matching to the comment above.

Patch by Marianne Mailhot-Sarrasin.

llvm-svn: 240556
2015-06-24 17:26:24 +00:00
Rafael Espindola 54c9f3da03 Simplify the logic, NFC.
llvm-svn: 240554
2015-06-24 17:08:44 +00:00
Daniel Sanders 110bf6da75 Eliminate additional redundant copies of Triple objects. NFC.
Subscribers: rafael, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10654

llvm-svn: 240540
2015-06-24 13:25:57 +00:00
Pawel Bylica cc35812877 Fix instruction scheduling live register tracking
Summary:
This patch fixes PR23405 (https://llvm.org/bugs/show_bug.cgi?id=23405).

During a node unscheduling an entry in LiveRegGens can be replaced with a new value. That corrupts the live reg tracking and LiveReg* structure is not cleared as should be during unscheduling. Problematic condition that enforces Gen replacement is `I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight()`. This condition should be checked only if LiveRegGen was set in current node unscheduling.

Test Plan: Regression test included.

Reviewers: hfinkel, atrick

Reviewed By: atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9993

llvm-svn: 240538
2015-06-24 12:49:42 +00:00
Zoran Jovanovic 67e04be640 [mips][microMIPS] Implement BREAK, EHB and EI instructions
http://reviews.llvm.org/D10090

llvm-svn: 240531
2015-06-24 10:32:16 +00:00
Rafael Espindola d7a32ea4b8 Change how symbol sizes are handled in lib/Object.
COFF and MachO only define symbol sizes for common symbols. Reflect that
in the class hierarchy by having a method for common symbols only in the base
and a general one in ELF.

This avoids the need of using a magic value for the size, which had a few
problems
* Most callers didn't check for it.
* The ones that did could not tell the magic value from a file actually having
  that value.

llvm-svn: 240529
2015-06-24 10:20:30 +00:00
Justin Bogner aa315fbb4c Hexagon: Paper over the undefined behaviour introduced by r238692
This stops shifting a 32-bit value by such absurd amounts as 96 and
120. We do this by dropping a call to the function that was doing this
entirely, which rather surprisingly doesn't break *any* tests.

I've also added an assert in the misbehaving function to prove that
it's no longer being called with completely invalid arguments.

This change looks pretty bogus and we should probably be reverting
r238692 instead, but this is hard to do with the number of follow ups
that have happened since. It can't be any worse than the undefined
behaviour that was happening before though.

llvm-svn: 240526
2015-06-24 07:03:07 +00:00
NAKAMURA Takumi c267b5f5aa MILexer.cpp: Try to fix a warning. [-Wsign-compare]
llvm-svn: 240525
2015-06-24 06:40:09 +00:00
Craig Topper a60ee86f60 [TableGen] Restore the use of the TheInit field in Record to cache the Record's DefInit. I broke this when I fixed memory leaks recently. Remove the DenseMap that mapped Record's to DefInit.
llvm-svn: 240524
2015-06-24 06:19:19 +00:00
Justin Bogner ee1247be7b Hexagon: Avoid left shifting negative values (it's UB)
Found by ubsan.

llvm-svn: 240521
2015-06-24 06:00:53 +00:00
Justin Bogner c97c48aadc SystemZ: Rephrase this allOnes calculation to avoid UB
This allOnes function hits undefined behaviour if Count is greater
than 64, but we can avoid that and simplify the calculation by just
saturating if such a value is passed in.

This comes up under ubsan becauseRxSBGOperands is sometimes created
with values that are 128 bits wide. Somebody more familiar with this
code should probably look into whether that's expected, as a 64 bit
mask may or may not be appropriate for such types.

llvm-svn: 240520
2015-06-24 05:59:19 +00:00
Ahmed Bougacha dd5da3e7ed [X86] Don't generate vbroadcasti128 for v4i64 splats from memory.
We used to erroneously match:
    (v4i64 shuffle (v2i64 load), <0,0,0,0>)

Whereas vbroadcasti128 is more like:
    (v4i64 shuffle (v2i64 load), <0,1,0,1>)

This problem doesn't exist for vbroadcastf128, which kept matching
the intrinsic after r231182.  We should perhaps re-introduce the
intrinsic here as well, but that's a separate issue still being
discussed.

While there, add some proper vbroadcastf128 tests.  We don't currently
match those, like for loading vbroadcastsd/ss on AVX (the reg-reg
broadcasts where added in AVX2).

Fixes PR23886.

llvm-svn: 240488
2015-06-24 00:07:16 +00:00
Pete Cooper a272f7fca9 Remove unused GlobalVariable::replaceUsesOfWithOnConstant. NFC.
The only caller of this method is Value::replaceAllUsesWith which
explicitly checks that we are not a GlobalValue.  So replace the
body with an unreachable to ensure that we never call it.

The unreachable itself is moved to GlobalValue not GlobalVariable
as that is the base class of all the globals we don't want to call
this method on.

Note, this patch is short lived as i'll soon refactor all callers
of this method.

llvm-svn: 240486
2015-06-24 00:05:07 +00:00
Alex Lorenz 240fc1e0aa MIR Serialization: Serialize immediate machine operands.
Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10573

llvm-svn: 240481
2015-06-23 23:42:28 +00:00
Sanjay Patel 6a24811d87 fix typo; NFC
llvm-svn: 240480
2015-06-23 23:26:22 +00:00
Sanjay Patel 9b7e6776a1 don't repeat function names in comments; NFC
llvm-svn: 240478
2015-06-23 23:05:08 +00:00
Alex Lorenz 51af160f4c MIR Parser: Use correct source locations for machine instruction diagnostics.
This commit translates the source locations for MIParser diagnostics from
the locations in the machine instruction string to the locations in the
MIR file.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10574

llvm-svn: 240474
2015-06-23 22:39:23 +00:00
Pete Cooper 86dd4cf5a1 Devirtualize Constant::destroyConstant.
This reorganizes destroyConstant and destroyConstantImpl.

Now there is only destroyConstant in Constant itself, while
subclasses are required to implement destroyConstantImpl.

destroyConstantImpl no longer calls delete but is instead only
responsible for removing the constant from any maps in which it
is contained.

Reviewed by Duncan Exon Smith.

llvm-svn: 240471
2015-06-23 21:55:11 +00:00
Alexey Samsonov 19ffcb900f Let llvm::ReplaceInstWithInst copy debug location from old to new instruction.
Currently some users of this function do this explicitly, and all the
rest forget to do this.

ThreadSanitizer was one of such users, and had missing debug
locations for calls into TSan runtime handling atomic operations,
eventually leading to poorly symbolized stack traces and malfunctioning
suppressions.

This is another change relevant to PR23837.

llvm-svn: 240460
2015-06-23 21:00:08 +00:00
Sanjoy Das 3f1bc3b2bb Revert "[FaultMaps] Move FaultMapParser to Object/"
This reverts commit r240364 (git c49542e5bb186).  The issue r240364 was
trying to fix was fixed independently in r240362.

llvm-svn: 240448
2015-06-23 20:09:03 +00:00
Mark Heffernan 9b536a640b This change fixes three bugs in loop unswitching. This change causes an 81% speed-up on a benchmark that is based on EigenConvolutionKernel2D from Eigen3, where the lack of loop unswitching blocks hoisting of loads out of a nested loop (see bug 23816 for how loop unswitching and load hoisting are related).
Change 1: Unswitching on trivial conditions should always happen regardless of the computed unswitching cost, as really the cost is zero. While there is code to make that happen, the logic that checks the unswitching cost against a threshold was moved to an earlier point (revision 147935) than the point where trivial unswitching is detected, so trivial unswitching is currently blocked by the cost threshold. This change fixes that.

Change 2: Before revision 147935 (from 2012-01-11), the threshold parameter was a per-loop threshold. So an unswitching happened only if the cost of the unswitching was less than the threshold. In an indirect way (and I believe unintentionally), the logic for this since then has been that the threshold is an over-all budget across all loops for all loop unswitching done by a given LoopUnswitch loop pass object. So if an unswitching with cost 100 happens in one function, that in effect reduces the threshold from 100 to 0 for the loops even in another function. This persists for the lifetime of that loop pass object. This makes no difference for most small examples but it is important for large examples. This revision fixes that.

Change 3: The cost is currently calculated as std::min(NumInstructions, 5 * NumBlocks). So a loop with 2 blocks and a million instructions will have an unswitching cost of 10. I changed this to just NumInstructions, as it were before revision 147935, though I'm open to e.g. instead replacing std::min with std::max.

I've tried to make the change minimally invasive while staying with what I think was the original intent of the code.
Submitted on behalf of broune@.

llvm-svn: 240438
2015-06-23 18:26:50 +00:00
Alex Lorenz 6f8a6be145 ADT: Add a string APSInt constructor.
This commit moves the APSInt initialization code that's used by
the LLLexer class into a new APSInt constructor that constructs
APSInts from strings.

This change is useful for MIR Serialization, as it would allow
the MILexer class to use the same APSInt initialization as 
LLexer when parsing immediate machine operands.

llvm-svn: 240436
2015-06-23 18:22:10 +00:00
Alex Lorenz 8955f7d704 AsmParser: Extend the API to make the global value and metadata node slot mappings publicly accessible.
This commit creates a new structure called 'SlotMapping' in the AsmParser library.
This structure can be passed into the public parsing APIs from the AsmParser library
in order to extract the data structures that map from slot numbers to unnamed global
values and metadata nodes.

This change is useful for MIR Serialization, as the MIR Parser has to lookup the
unnamed global values and metadata nodes by their slot numbers.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10551

llvm-svn: 240427
2015-06-23 17:10:10 +00:00
Alex Lorenz f3db51de5e MIR Serialization: Serialize physical register machine operands.
This commit introduces functionality that's used to serialize machine operands.
Only the physical register operands are serialized by this commit.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10525

llvm-svn: 240425
2015-06-23 16:35:26 +00:00
John Brawn d86e004b7e [ARM] ARMLoadStoreOpt::UpdateBaseRegUses should stop on def
When UpdateBaseRegUses sees an instruction that defines the base
register it must stop, as the base register value it is updating is no
longer live. Ideally we would already have seen the register be killed
(which is already checked for), but the kill flags may be inaccurate
and we have to account for this.

Differential Revision: http://reviews.llvm.org/D10566

llvm-svn: 240424
2015-06-23 16:02:11 +00:00
Justin Bogner a6d383677d SystemZ: Avoid left shifting negative values (it's UB)
Found by ubsan.

llvm-svn: 240420
2015-06-23 15:38:24 +00:00
Benjamin Kramer 49381bee2e [Option] Plug a leak when move-assigning an InputArgList.
The class has a non-trivial dtor so we have to clean up before we move
in new members. Remove misleading comment as a default move assignment
operator will never be synthesized for this class.

llvm-svn: 240417
2015-06-23 15:28:10 +00:00
Benjamin Kramer e7800cab82 Make helper functions static. NFC.
llvm-svn: 240416
2015-06-23 14:51:40 +00:00
Benjamin Kramer 8c57cfd51b [BranchFolding] Document why replacing HashMachineInstr with hash_code doesn't work
llvm-svn: 240415
2015-06-23 14:47:36 +00:00
Benjamin Kramer 6b568964ba [MachineBasicBlock] Add getFirstNonDebugInstr to complement getLastNonDebugInstr
Use it in CodeGen where applicable. No functionality change intended.

llvm-svn: 240414
2015-06-23 14:47:29 +00:00
Benjamin Kramer 9c956b33d7 [MachineBasicBlock] Use the const_cast(this) trick to reduce duplication
NFC.

llvm-svn: 240413
2015-06-23 14:47:18 +00:00
Rafael Espindola 6763f5a43e Be sure to set the DataLayout before checking the cache.
This makes sure the same mangling is used.

Should fix the OS X bots.

llvm-svn: 240411
2015-06-23 14:42:34 +00:00
Toma Tabacu d88d79c79d [mips] [IAS] Add partial support for the ULHU pseudo-instruction.
Summary:
This only adds support for ULHU of an immediate address with/without a source register.
It does not include support for ULHU of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9671

llvm-svn: 240410
2015-06-23 14:39:42 +00:00
Rafael Espindola 8c5f537f18 Remove unused arguments and move ManglerPrefixTy to the implementation.
llvm-svn: 240408
2015-06-23 14:11:09 +00:00
Toma Tabacu 0b3e97874d [mips] [IAS] Add support for generating DADDu to createAddu(). NFC.
Summary: This isn't used right now, but it will be in some upcoming changes.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10568

llvm-svn: 240407
2015-06-23 14:00:54 +00:00
Rafael Espindola c233f74e6e Simplify the Mangler interface now that DataLayout is mandatory.
We only need to pass in a DataLayout when mangling a raw string, not when
constructing the mangler.

llvm-svn: 240405
2015-06-23 13:59:29 +00:00
Petar Jovanovic b7915a1f0b [mips64] Emit correct addend for some PC-relative relocations
So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch
fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation.

Patch by Vladimir Radosavljevic.

Differential Revision: http://reviews.llvm.org/D10565

llvm-svn: 240404
2015-06-23 13:54:42 +00:00
Krzysztof Parzyszek c3966017b9 [Hexagon] Use MF reference from parent class in HexagonPacketizerList
llvm-svn: 240403
2015-06-23 13:50:23 +00:00
Toma Tabacu bfcbfd56af [mips] [IAS] Move some function definitions to MipsTargetStreamer.cpp. NFC.
Summary: For the sake of consistency and to make some upcoming changes a little less noisy.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10639

llvm-svn: 240398
2015-06-23 12:34:19 +00:00
Rafael Espindola ce4c2bc1d6 Use MCSymbols for FastISel.
The summary is that it moves the mangling earlier and replaces a few
calls to .addExternalSymbol with addSym.

I originally wanted to replace all the uses of addExternalSymbol with
addSym, but noticed it was a lot of work and doesn't need to be done
all at once.

llvm-svn: 240395
2015-06-23 12:21:54 +00:00
Daniel Jasper 41de8027b1 Revert r240302 ("Bring r240130 back.").
This causes errors like:

  ld: error: blah.o: requires dynamic R_X86_64_PC32 reloc against '' which
  may overflow at runtime; recompile with -fPIC
  blah.cc:function f(): error: undefined reference to ''
  blah.o:g(): error: undefined reference to ''

I have not yet come up with an appropriate reproduction.

llvm-svn: 240394
2015-06-23 11:31:32 +00:00
Alexander Kornienko f00654e31b Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)
Apparently, the style needs to be agreed upon first.

llvm-svn: 240390
2015-06-23 09:49:53 +00:00
Elena Demikhovsky 5e2f8c4231 AVX-512: Added all forms of VPABS instruction
Added all intrinsics, tests for encoding, tests for intrinsics.

llvm-svn: 240386
2015-06-23 08:19:46 +00:00
Justin Bogner c16021514c MCExpr: Avoid UB by evaluating this shift as unsigned
We hit undefined behaviour in some MCExpr tests when the LHS of a left
shift is -1. Twos-complement semantics are completely reasonable here,
so we should just do the shift in unsigned.

llvm-svn: 240385
2015-06-23 07:32:55 +00:00
Justin Bogner 6499b5f086 [mips] Fix some UB by shifting before sign-extending
Avoid shifting a negative value by sign-extending after the shift.

Fixes a couple of tests that were failing under ubsan.

llvm-svn: 240381
2015-06-23 07:28:57 +00:00
Weiming Zhao f1abad57da Fix PR13851: Preserve metadata for the unswitched branch
This patch copies the metadata of the unswitched branch to the newly
crreated branch in loop unswitch pass.

llvm-svn: 240378
2015-06-23 05:31:09 +00:00
Rafael Espindola 49943652f5 Handle multiple symbols having the same address.
I will add an explicit test in a second, but this fixes the bots.

llvm-svn: 240372
2015-06-23 03:36:08 +00:00
David Majnemer 726901b638 [InstCombine] Optimize subtract of selects into a select of a sub
This came up when examining some code generated by clang's IRGen for
certain member pointers.

llvm-svn: 240369
2015-06-23 02:49:24 +00:00
Rafael Espindola b109c032bd Extract an utility for computing symbol sizes on MachO and COFF.
I will add a second user in the next commit.

llvm-svn: 240366
2015-06-23 02:08:48 +00:00
Matt Arsenault 0b554ed364 AMDGPU: Use getAsInteger instead of atoi
llvm-svn: 240365
2015-06-23 02:05:55 +00:00
Sanjoy Das 9d95716c15 [FaultMaps] Move FaultMapParser to Object/
Summary:
That way llvm-objdump can rely on it without adding an extra dependency
on CodeGen.

This change duplicates the FaultKind enum and the code that serializes
it to a string.  I could not figure out a way to get around this without
adding a new dependency to Object

Reviewers: rafael, ab

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10619

llvm-svn: 240364
2015-06-23 01:05:26 +00:00
Sanjay Patel e79b43a01f [x86] generalize reassociation optimization in machine combiner to 2 instructions
Currently ( D10321, http://reviews.llvm.org/rL239486 ), we can use the machine combiner pass
to reassociate the following sequence to reduce the critical path:

A = ? op ?
B = A op X
C = B op Y
-->
A = ? op ?
B = X op Y
C = A op B

'op' is currently limited to x86 AVX scalar FP adds (with fast-math on), but in theory, it could
be any associative math/logic op (see TODO in code comment).

This patch generalizes the pattern match to ignore the instruction that defines 'A'. So instead of
a sequence of 3 adds, we now only need to find 2 dependent adds and decide if it's worth
reassociating them.

This generalization has a compile-time cost because we can now match more instruction sequences
and we rely more heavily on the machine combiner to discard sequences where reassociation doesn't
improve the critical path.

For example, in the new test case:

A = M div N
B = A add X
C = B add Y

We'll match 2 reassociation patterns, but this transform doesn't reduce the critical path:

A = M div N
B = A add Y
C = B add X

We need the combiner to reject that pattern but select this:

A = M div N
B = X add Y
C = B add A

Differential Revision: http://reviews.llvm.org/D10460

llvm-svn: 240361
2015-06-23 00:39:40 +00:00
Justin Bogner 3a7d44cb81 Re-apply "InstrProf: When reading, copy the data instead of taking a reference. NFC"
This version fixes a missing include that MSVC noticed and
clarifies the ownership of the counter buffer that's passed to
InstrProfRecord.

This restores r240206, which was reverted in r240208.

Patch by Betul Buyukkurt.

llvm-svn: 240360
2015-06-22 23:58:05 +00:00
Evgeniy Stepanov 9e0d41ab09 Fix PR23914.
r226830 moved the declaration of Buf to a nested scope, resulting
in a dangling reference (in StringRef Name), and a use-after-free.

llvm-svn: 240357
2015-06-22 23:36:03 +00:00
Logan Chien 9d5891fd34 Code cleanup: Remove std::move() around xvalue (NFC)
Remove std::move() around xvalue so that copy elision is eligible.
In case that copy elision is not appliable, the c++ standard also
guarantees the move semantics on xvalue.  Thus, it is not necessary
to wrap Args with std::move.

This also silence a warning since r240345.

llvm-svn: 240355
2015-06-22 23:16:02 +00:00
Adam Nemet f530b329c7 [LoopDist] Improve variable names and comments in LoopVersioning class, NFC
As with the previous patch, the goal is to turn the class into a general
loop-versioning class.  This patch removes any references to loop
distribution.

llvm-svn: 240352
2015-06-22 22:59:40 +00:00
David Blaikie db3d31d0be Modify ParseArgs to return the InputArgList by value - there's no need for dynamic allocation/ownership here
The one caller that does anything other than keep this variable on the
stack is the single use of DerivedArgList in Clang, which is a bit more
interesting but can probably be cleaned up/simplified a bit further
(have DerivedArgList take ownership of the InputArgList rather than
needing to reference its Args indirectly) which I'll try to after this.

llvm-svn: 240345
2015-06-22 22:06:37 +00:00
Pawel Bylica e6fd8c4232 Revert r240291: causes problems in self-hosted builds.
llvm-svn: 240343
2015-06-22 21:54:07 +00:00
Simon Pilgrim 616fe5066a [X86][FMA4] FMA4 ops can perform unaligned folded loads.
llvm-svn: 240342
2015-06-22 21:49:41 +00:00
Peter Collingbourne ea45d834e0 Linker: Do not expect comdat to exist in source module.
llvm-svn: 240341
2015-06-22 21:46:51 +00:00
Joseph Tremoulet 771f4d9d97 Fix line endings (NFC)
I inadvertently checked these in with Windows-style line
endings in r240288.

llvm-svn: 240340
2015-06-22 21:37:34 +00:00
Frederic Riss ebc162a766 [Object] Search for architecures by name in MachOUniversalBinary::getObjectForArch()
The reason we need to search by name rather than by Triple::ArchType
is to handle subarchitecture correclty. There is no different ArchType
for the x86_64h architecture (it identifies itself as x86_64), or for
the various ARM subarches. The only way to get to the subarch slice
in an universal binary is to search by name.

This issue led to hard to debug and transient symbolication failures
in Asan tests (it mostly works, because the files are very similar).

This also affects the Profiling infrastucture as it is the other user
of that API.

Reviewers: samsonov, bogner

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10604

llvm-svn: 240339
2015-06-22 21:33:24 +00:00
Tom Stellard f0296cee9b R600/SI: Use ELF64 format instead of ELF32
Reviewers: arsenm, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10392

llvm-svn: 240331
2015-06-22 21:03:54 +00:00
Tom Stellard 3aed34e947 R600: Use EM_AMDGPU for the ELF Machine type
Reviewers: arsenm, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10390

llvm-svn: 240330
2015-06-22 21:03:52 +00:00
Ahmed Bougacha ed3c4d1a3d [X86] Teach load folding to accept scalar _Int users of MOVSS/MOVSD.
The _Int instructions are special, in that they operate on the full
VR128 instead of FR32.  The load folding then looks at MOVSS, at the
user, and bails out when it sees a size mismatch.

What we really know is that the rm_Int instructions don't load the
higher lanes, so folding is fine.

This happens for the straightforward intrinsic code, e.g.:

    _mm_add_ss(a, _mm_load_ss(p));

Fixes PR23349.

Differential Revision: http://reviews.llvm.org/D10554

llvm-svn: 240326
2015-06-22 20:51:51 +00:00
Alex Lorenz 91370c5d62 MIR Serialization: Introduce a lexer for machine instructions.
This commit adds a function that tokenizes the string containing
the machine instruction. This commit also adds a struct called 
'MIToken' which is used to represent the lexer's tokens.

Reviewers: Sean Silva

Differential Revision: http://reviews.llvm.org/D10521

llvm-svn: 240323
2015-06-22 20:37:46 +00:00