02c1b54a4a
[SelectionDAG] Generalised the CONCAT_VECTORS creation to support BUILD_VECTOR and UNDEF folding.
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llvm-svn: 258646
2016-01-23 22:27:54 +00:00
e6955f3211
[X86][SSE] Ensure BLENDPD/BLENDPS/PBLEND inputs are both of the correct input type
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llvm-svn: 256782
2016-01-04 21:41:11 +00:00
d5c2d287f9
[X86, AVX] use blends instead of insert128 with index 0
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Another case of x86-specific shuffle strength reduction:
avoid generating insert*128 instructions with index 0 because
they are slower than their non-lane-changing blend equivalents.
Shuffle lowering already catches most of these cases, but
the zero vector case and some other paths such as in the
modified test in vector-shuffle-256-v32.ll were getting
through.
Differential Revision: http://reviews.llvm.org/D8366
llvm-svn: 232773
2015-03-19 22:29:40 +00:00
11ce908e4c
fixed to test feature, not CPU
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llvm-svn: 232398
2015-03-16 18:24:28 +00:00
a8ec726bb6
add CHECK-LABELs for more reliable testing
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llvm-svn: 232391
2015-03-16 17:59:07 +00:00
12b72def4e
Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled.
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llvm-svn: 145376
2011-11-29 05:37:58 +00:00
76bc28bac6
Add patterns to generate copies for extract_subvector instead of
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using vextractf128. This will reduce the number of issued instruction
for several avx codes.
llvm-svn: 136323
2011-07-28 01:26:50 +00:00
eca99c4b5a
Add a few patterns to match allzeros without having to use the fp unit.
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Take advantage that the 128-bit vpxor zeros the higher part and use it.
This also fixes PR10491
llvm-svn: 136321
2011-07-28 01:26:43 +00:00
14a95bda04
Although we already support this, add testcases for consistency
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llvm-svn: 135728
2011-07-22 00:15:03 +00:00
91eff5140f
Add a DAGCombine for transforming 128->256 casts into a simple
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vxorps + vinsertf128 pair of instructions
llvm-svn: 135727
2011-07-22 00:15:00 +00:00
Simon Pilgrim