Commit Graph

474 Commits

Author SHA1 Message Date
Chris Lattner 34ed27c46d clarify a comment, thanks Duncan.
llvm-svn: 46313
2008-01-24 17:10:01 +00:00
Chris Lattner e97fa8cdf0 Fix this buggy transformation. Two observations:
1. we already know the value is dead, so don't bother replacing 
   it with undef.
2. The very case the comment describes actually makes the load
   live which asserts in deletenode.  If we do the replacement
   and the node becomes live, just treat it as new.  This fixes
   a failure on X86/2008-01-16-InvalidDAGCombineXform.ll with
   some local changes in my tree.

llvm-svn: 46306
2008-01-24 07:57:06 +00:00
Chris Lattner d66eac62fd The dag combiner is missing revisiting nodes that it really should, and thus leaving
dead stuff around.  This gets fed into the isel pass and causes certain foldings from
happening because nodes have extraneous uses floating around.  For example, if we turned
foo(bar(x)) -> baz(x), we sometimes left bar(x) around.

llvm-svn: 46305
2008-01-24 07:18:21 +00:00
Chris Lattner 0feb1b0f84 fold fp_round(fp_round(x)) -> fp_round(x).
llvm-svn: 46304
2008-01-24 06:45:35 +00:00
Chris Lattner 1ea55cf816 This commit changes:
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret

llvm-svn: 46140
2008-01-17 19:59:44 +00:00
Chris Lattner 7eabed3521 code cleanups, no functionality change.
llvm-svn: 46126
2008-01-17 07:20:38 +00:00
Chris Lattner 72733e573b * Introduce a new SelectionDAG::getIntPtrConstant method
and switch various codegen pieces and the X86 backend over
  to using it.

* Add some comments to SelectionDAGNodes.h

* Introduce a second argument to FP_ROUND, which indicates
  whether the FP_ROUND changes the value of its input. If
  not it is safe to xform things like fp_extend(fp_round(x)) -> x.

llvm-svn: 46125
2008-01-17 07:00:52 +00:00
Evan Cheng 7be1528004 Fixes a nasty dag combiner bug that causes a bunch of tests to fail at -O0.
It's not safe to use the two value CombineTo variant to combine away a dead load.
e.g. 
v1, chain2 = load chain1, loc
v2, chain3 = load chain2, loc
v3         = add v2, c 
Now we replace use of v1 with undef, use of chain2 with chain1.
ReplaceAllUsesWith() will iterate through uses of the first load and update operands:
v1, chain2 = load chain1, loc
v2, chain3 = load chain1, loc
v3         = add v2, c 
Now the second load is the same as the first load, SelectionDAG cse will ensure
the use of second load is replaced with the first load.
v1, chain2 = load chain1, loc
v3         = add v1, c
Then v1 is replaced with undef and bad things happen.

llvm-svn: 46099
2008-01-16 23:11:54 +00:00
Chris Lattner 2e50a6f90f Factor the ReachesChainWithoutSideEffects out of dag combiner into
a public SDOperand::reachesChainWithoutSideEffects method.  No 
functionality change.

llvm-svn: 46050
2008-01-16 05:49:24 +00:00
Chris Lattner 51b01bf8a5 Make load->store deletion a bit smarter. This allows us to compile this:
void test(long long *P) { *P ^= 1; }

into just:

_test:
	movl	4(%esp), %eax
	xorl	$1, (%eax)
	ret

instead of code like this:

_test:
	movl	4(%esp), %ecx
        xorl    $1, (%ecx)
	movl	4(%ecx), %edx
	movl	%edx, 4(%ecx)
	ret

llvm-svn: 45762
2008-01-08 23:08:06 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Chris Lattner 2de9b85297 make sure not to zap volatile stores, thanks a lot to Dale for noticing this!
llvm-svn: 45402
2007-12-29 07:15:45 +00:00
Chris Lattner 5919b48fe9 don't fold fp_round(fp_extend(load)) -> fp_round(extload)
llvm-svn: 45400
2007-12-29 06:55:23 +00:00
Chris Lattner 3f9c6a7260 Delete a store whose input is a load from the same pointer:
x = load p
  store x -> p

llvm-svn: 45398
2007-12-29 06:26:16 +00:00
Chris Lattner efd1cddb5a Tell TargetLoweringOpt whether it is running before
or after legalize.

llvm-svn: 45321
2007-12-22 20:56:36 +00:00
Evan Cheng 9f06e5e2df Don't leave newly created nodes around if it turns out they are not needed.
llvm-svn: 45186
2007-12-19 01:34:38 +00:00
Dale Johannesen 5eff4de9c8 Redo previous patch so optimization only done for i1.
Simpler and safer.

llvm-svn: 44663
2007-12-06 17:53:31 +00:00
Chris Lattner eedaf92fcf third time around: instead of disabling this completely,
only disable it if we don't know it will be obviously profitable.
Still fixme, but less so. :)

llvm-svn: 44658
2007-12-06 07:47:55 +00:00
Chris Lattner b5fdfb9612 Actually, disable this code for now. More analysis and improvements to
the X86 backend are needed before this should be enabled by default.

llvm-svn: 44657
2007-12-06 07:44:31 +00:00
Chris Lattner 7c709a5d08 implement a readme entry, compiling the code into:
_foo:
	movl	$12, %eax
	andl	4(%esp), %eax
	movl	_array(%eax), %eax
	ret

instead of:

_foo:
	movl	4(%esp), %eax
	shrl	$2, %eax
	andl	$3, %eax
	movl	_array(,%eax,4), %eax
	ret

As it turns out, this triggers all the time, in a wide variety of
situations, for example, I see diffs like this in various programs:

-       movl    8(%eax), %eax
-       shll    $2, %eax
-       andl    $1020, %eax
-       movl    (%esi,%eax), %eax
+       movzbl  8(%eax), %eax
+       movl    (%esi,%eax,4), %eax


-       shll    $2, %edx
-       andl    $1020, %edx
-       movl    (%edi,%edx), %edx
+       andl    $255, %edx
+       movl    (%edi,%edx,4), %edx

Unfortunately, I also see stuff like this, which can be fixed in the
X86 backend:

-       andl    $85, %ebx
-       addl    _bit_count(,%ebx,4), %ebp
+       shll    $2, %ebx
+       andl    $340, %ebx
+       addl    _bit_count(%ebx), %ebp

llvm-svn: 44656
2007-12-06 07:33:36 +00:00
Dale Johannesen 05bbbda78a Fix PR1842.
llvm-svn: 44649
2007-12-06 01:43:46 +00:00
Dan Gohman 9a69341725 Don't lower srem/urem X%C to X-X/C*C unless the division is actually
optimized. This avoids creating illegal divisions when the combiner is
running after legalize; this fixes PR1815. Also, it produces better
code in the included testcase by avoiding the subtract and multiply
when the division isn't optimized.

llvm-svn: 44341
2007-11-26 23:46:11 +00:00
Duncan Sands e795efea5b Move MinAlign to MathExtras.h.
llvm-svn: 43944
2007-11-09 13:41:39 +00:00
Duncan Sands e7a9ac929f Fix some load/store logic that would be wrong for
apints on big-endian machines if the bitwidth is
not a multiple of 8.  Introduce a new helper,
MVT::getStoreSizeInBits, and use it.

llvm-svn: 43934
2007-11-09 08:57:19 +00:00
Evan Cheng ece4c68b82 If both parts of smul_lohi, etc. are used, don't simplify. If only one part is used, try simplify it.
llvm-svn: 43888
2007-11-08 09:25:29 +00:00
Evan Cheng 0747bc1df6 Typo.
llvm-svn: 43511
2007-10-30 20:11:21 +00:00
Dan Gohman ae95d72a52 Fix a DAGCombiner abort on a bitcast from a scalar to a vector.
llvm-svn: 43470
2007-10-29 20:44:42 +00:00
Evan Cheng e106e2f142 Enable more fold (sext (load x)) -> (sext (truncate (sextload x)))
transformation. Previously, it's restricted by ensuring the number of load uses
is one. Now the restriction is loosened up by allowing setcc uses to be
"extended" (e.g. setcc x, c, eq -> setcc sext(x), sext(c), eq).

llvm-svn: 43465
2007-10-29 19:58:20 +00:00
Duncan Sands 1826deda68 The guaranteed alignment of ptr+offset is only the minimum of
of offset and the alignment of ptr if these are both powers of
2.  While the ptr alignment is guaranteed to be a power of 2,
there is no reason to think that offset is.  For example, if
offset is 12 (the size of a long double on x86-32 linux) and
the alignment of ptr is 8, then the alignment of ptr+offset
will in general be 4, not 8.  Introduce a function MinAlign,
lifted from gcc, for computing the minimum guaranteed alignment.
I've tried to fix up everywhere under lib/CodeGen/SelectionDAG/.
I also changed some places that weren't wrong (because both values
were a power of 2), as a defensive change against people copying
and pasting the code.
Hopefully someone who cares about alignment will review the rest
of LLVM and fix up the remaining places.  Since I'm on x86 I'm
not very motivated to do this myself...

llvm-svn: 43421
2007-10-28 12:59:45 +00:00
Dale Johannesen 6802d0c96f Redo "last ppc long double fix" as Chris wants.
llvm-svn: 43189
2007-10-19 20:29:00 +00:00
Dale Johannesen 10432e5a67 More ppcf128 issues (maybe the last)?
llvm-svn: 43160
2007-10-19 00:59:18 +00:00
Dale Johannesen e5facd51cb Disable attempts to constant fold PPC f128.
Remove the assumption that this will happen from
various places.

llvm-svn: 43053
2007-10-16 23:38:29 +00:00
Chris Lattner 3cfb56d489 One mundane change: Change ReplaceAllUsesOfValueWith to *optionally*
take a deleted nodes vector, instead of requiring it.

One more significant change:  Implement the start of a legalizer that
just works on types.  This legalizer is designed to run before the 
operation legalizer and ensure just that the input dag is transformed
into an output dag whose operand and result types are all legal, even
if the operations on those types are not.

This design/impl has the following advantages:

1. When finished, this will *significantly* reduce the amount of code in
   LegalizeDAG.cpp.  It will remove all the code related to promotion and
   expansion as well as splitting and scalarizing vectors.
2. The new code is very simple, idiomatic, and modular: unlike 
   LegalizeDAG.cpp, it has no 3000 line long functions. :)
3. The implementation is completely iterative instead of recursive, good
   for hacking on large dags without blowing out your stack.
4. The implementation updates nodes in place when possible instead of 
   deallocating and reallocating the entire graph that points to some 
   mutated node.
5. The code nicely separates out handling of operations with invalid 
   results from operations with invalid operands, making some cases
   simpler and easier to understand.
6. The new -debug-only=legalize-types option is very very handy :), 
   allowing you to easily understand what legalize types is doing.

This is not yet done.  Until the ifdef added to SelectionDAGISel.cpp is
enabled, this does nothing.  However, this code is sufficient to legalize
all of the code in 186.crafty, olden and freebench on an x86 machine.  The
biggest issues are:

1. Vectors aren't implemented at all yet
2. SoftFP is a mess, I need to talk to Evan about it.
3. No lowering to libcalls is implemented yet.
4. Various operations are missing etc.
5. There are FIXME's for stuff I hax0r'd out, like softfp.

Hey, at least it is a step in the right direction :).  If you'd like to help,
just enable the #ifdef in SelectionDAGISel.cpp and compile code with it.  If
this explodes it will tell you what needs to be implemented.  Help is 
certainly appreciated.

Once this goes in, we can do three things:

1. Add a new pass of dag combine between the "type legalizer" and "operation
   legalizer" passes.  This will let us catch some long-standing isel issues
   that we miss because operation legalization often obfuscates the dag with
   target-specific nodes.
2. We can rip out all of the type legalization code from LegalizeDAG.cpp,
   making it much smaller and simpler.  When that happens we can then 
   reimplement the core functionality left in it in a much more efficient and
   non-recursive way.
3. Once the whole legalizer is non-recursive, we can implement whole-function
   selectiondags maybe...

llvm-svn: 42981
2007-10-15 06:10:22 +00:00
Chris Lattner f47e30627a Enhance the truncstore optimization code to handle shifted
values and propagate demanded bits through them in simple cases.

This allows this code:
void foo(char *P) {
   strcpy(P, "abc");
}
to compile to:

_foo:
        ldrb r3, [r1]
        ldrb r2, [r1, #+1]
        ldrb r12, [r1, #+2]!
        ldrb r1, [r1, #+1]
        strb r1, [r0, #+3]
        strb r2, [r0, #+1]
        strb r12, [r0, #+2]
        strb r3, [r0]
        bx lr

instead of:

_foo:
        ldrb r3, [r1, #+3]
        ldrb r2, [r1, #+2]
        orr r3, r2, r3, lsl #8
        ldrb r2, [r1, #+1]
        ldrb r1, [r1]
        orr r2, r1, r2, lsl #8
        orr r3, r2, r3, lsl #16
        strb r3, [r0]
        mov r2, r3, lsr #24
        strb r2, [r0, #+3]
        mov r2, r3, lsr #16
        strb r2, [r0, #+2]
        mov r3, r3, lsr #8
        strb r3, [r0, #+1]
        bx lr

testcase here: test/CodeGen/ARM/truncstore-dag-combine.ll

This also helps occasionally for X86 and other cases not involving 
unaligned load/stores.

llvm-svn: 42954
2007-10-13 06:58:48 +00:00
Chris Lattner 5e6fe054a2 Add a simple optimization to simplify the input to
truncate and truncstore instructions, based on the 
knowledge that they don't demand the top bits.

llvm-svn: 42952
2007-10-13 06:35:54 +00:00
Duncan Sands 56ab90d3ad Correct swapped arguments to getConstant.
llvm-svn: 42824
2007-10-10 09:54:50 +00:00
Dan Gohman 5c6d0c3b99 DAGCombiner support for UDIVREM/SDIVREM and UMUL_LOHI/SMUL_LOHI.
Check if one of the two results unneeded so see if a simpler operator
could bs used. Also check to see if each of the two computations could be
simplified if they were split into separate operators. Factor out the code
that calls visit() so that it can be used for this purpose.

llvm-svn: 42759
2007-10-08 17:57:15 +00:00
Evan Cheng 0de312dd7d Reapply 42677.
llvm-svn: 42692
2007-10-06 08:19:55 +00:00
Chris Lattner 82217bd155 revert evan's patch until the header is committed
llvm-svn: 42686
2007-10-06 06:08:17 +00:00
Evan Cheng f4b5d491df Added DAG xforms. e.g.
(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.

llvm-svn: 42677
2007-10-06 02:46:29 +00:00
Evan Cheng e2e8f2d96b Fix a bogus splat xform:
shuffle <undef, undef, x, undef>, <undef, undef, undef, undef>, <2, 2, 2, 2>
!=
<undef, undef, x, undef>

llvm-svn: 42111
2007-09-18 21:54:37 +00:00
Dale Johannesen af12b57405 Prevent crash on long double.
llvm-svn: 42103
2007-09-18 18:36:59 +00:00
Dale Johannesen 028084efe5 Revise previous patch per review comments.
Next round of x87 long double stuff.
Getting close now, basically works.

llvm-svn: 41875
2007-09-12 03:30:33 +00:00
Dale Johannesen 245dceb06d Add APInt interfaces to APFloat (allows directly
access to bits).  Use them in place of float and
double interfaces where appropriate.
First bits of x86 long double constants handling 
(untested, probably does not work).

llvm-svn: 41858
2007-09-11 18:32:33 +00:00
Chris Lattner 58c227bd09 Emit:
cmpl    %eax, %ecx
        setae   %al
        movzbl  %al, %eax

instead of:

        cmpl    %eax, %ecx
        setb    %al
        xorb    $1, %al
        movzbl  %al, %eax

when using logical not of a C comparison.

llvm-svn: 41807
2007-09-10 21:39:07 +00:00
Dale Johannesen 446b900192 Add mod, copysign, abs operations to APFloat.
Implement some constant folding in SelectionDAG and
DAGCombiner using APFloat.  Remove double versions
of constructor and getValue from ConstantFPSDNode.

llvm-svn: 41664
2007-08-31 23:34:27 +00:00
Dan Gohman 9625d812c9 Make DAGCombiner's global alias analysis query more precise in the case
where both pointers have non-zero offsets.

llvm-svn: 41491
2007-08-27 16:32:11 +00:00
Dale Johannesen b6d2bec418 Revise per review comments.
llvm-svn: 41409
2007-08-26 01:18:27 +00:00
Dale Johannesen 2cfcf70f82 Add APFloat interface to ConstantFPSDNode. Change
over uses in DAGCombiner.  Fix interfaces to work
with APFloats.

llvm-svn: 41407
2007-08-25 22:10:57 +00:00
Evan Cheng f5a23abf37 Fold C ? 0 : 1 to ~C or zext(~C) or trunc(~C) depending the types.
llvm-svn: 41163
2007-08-18 05:57:05 +00:00
Dan Gohman 30f060be80 Fix the alias analysis query in DAGCombiner to not add in two
offsets. The SrcValueOffset values are the real offsets from the
SrcValue base pointers.

llvm-svn: 40534
2007-07-26 16:14:06 +00:00
Dan Gohman 80f9f077e3 Don't call SimplifyVBinOp for non-vector operations, following earlier review
feedback. This theoretically makes the common (scalar) case more efficient.

llvm-svn: 39823
2007-07-13 20:03:40 +00:00
Dan Gohman adb3d37c07 Fix a bug in the folding of binary operators to undef.
Thanks to Lauro for spotting this!

llvm-svn: 38491
2007-07-10 15:19:29 +00:00
Dan Gohman fa91282dbf Fix the folding of undef in several binary operators to recognize
undef in either the left or right operand.

llvm-svn: 38489
2007-07-10 14:20:37 +00:00
Dan Gohman 2af3063337 Preserve volatililty and alignment information when lowering or
simplifying loads and stores.

llvm-svn: 38473
2007-07-09 22:18:38 +00:00
Chris Lattner 6caf8fdd04 Fix this warning:
DAGCombiner.cpp: In member function 'llvm::SDOperand<unnamed>::DAGCombiner::visitOR(llvm::SDNode*)':
DAGCombiner.cpp:1608: warning: passing negative value '-0x00000000000000001' for argument 1 to 'llvm::SDOperand llvm::SelectionDAG::getConstant(uint64_t, llvm::MVT::ValueType, bool)'

oiy.

llvm-svn: 38458
2007-07-09 16:16:34 +00:00
Dan Gohman 06563a8702 Fix several over-aggressive folds for undef nodes in dagcombine, to
follow the rules for undef used in instcombine.

llvm-svn: 37851
2007-07-03 14:03:57 +00:00
Dan Gohman 9a70823375 Teach GetNegatedExpression to negate 0-B to B in UnsafeFPMath mode, and
visitFSUB to fold 0-B to -B in UnsafeFPMath mode. Also change visitFNEG
to use isNegatibleForFree/GetNegatedExpression instead of doing a subset
of the same thing manually.

This fixes test/CodeGen/X86/negative-sin.ll.

llvm-svn: 37842
2007-07-02 15:48:56 +00:00
Dan Gohman a866514528 Generalize MVT::ValueType and associated functions to be able to represent
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719
2007-06-25 16:23:39 +00:00
Dan Gohman 309d3d51b3 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
2007-06-22 14:59:07 +00:00
Evan Cheng aa5f5d960d Xforms:
(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))

llvm-svn: 37685
2007-06-21 07:39:16 +00:00
Dan Gohman a7644dd9b9 Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.

llvm-svn: 37656
2007-06-19 14:13:56 +00:00
Dan Gohman 5c4413120f Rename MVT::getVectorBaseType to MVT::getVectorElementType.
llvm-svn: 37579
2007-06-14 22:58:02 +00:00
Chris Lattner 4698083b96 tighten up recursion depth again
llvm-svn: 37330
2007-05-25 02:19:06 +00:00
Evan Cheng a4d187b8ce Fix a typo that caused combiner to create mal-formed pre-indexed store where value store is the same as the base pointer.
llvm-svn: 37318
2007-05-24 02:35:39 +00:00
Chris Lattner 6509c0673f prevent exponential recursion in isNegatibleForFree
llvm-svn: 37310
2007-05-23 07:35:22 +00:00
Dan Gohman b539df3389 Qualify calls to getTypeForValueType with MVT:: too.
llvm-svn: 37233
2007-05-18 18:41:29 +00:00
Dale Johannesen 7a6c175e7a Don't fold bitconvert(load) for preinc/postdec loads. Likewise stores.
llvm-svn: 37130
2007-05-16 22:45:30 +00:00
Chris Lattner 48fb92f75d Use a ptr set instead of a linear search to unique TokenFactor operands.
This fixes PR1423

llvm-svn: 37102
2007-05-16 06:37:59 +00:00
Evan Cheng 288f133c71 Bug fix: should check ABI alignment, not pref. alignment.
llvm-svn: 37094
2007-05-16 02:04:50 +00:00
Lauro Ramos Venancio 3f142cbca2 Fix an infinite recursion in GetNegatedExpression.
llvm-svn: 37086
2007-05-15 17:05:43 +00:00
Chris Lattner e49c974a7c implement a simple fneg optimization/propagation thing. This compiles:
CodeGen/PowerPC/fneg.ll into:

_t4:
        fmul f0, f3, f4
        fmadd f1, f1, f2, f0
        blr

instead of:

_t4:
        fneg f0, f3
        fmul f0, f0, f4
        fmsub f1, f1, f2, f0
        blr

llvm-svn: 37054
2007-05-14 22:04:50 +00:00
Evan Cheng f325c2a65e Can't fold the bit_convert is the store is a truncating store.
llvm-svn: 36962
2007-05-09 21:49:47 +00:00
Evan Cheng 562e45692e Forgot a check.
llvm-svn: 36910
2007-05-07 21:36:06 +00:00
Evan Cheng a4cf58a103 Enable a couple of xforms:
- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment

llvm-svn: 36908
2007-05-07 21:27:48 +00:00
Evan Cheng 044a0a8cfb Don't create indexed load / store with zero offset!
llvm-svn: 36716
2007-05-03 23:52:19 +00:00
Evan Cheng b68343cdd8 Forgot about chain result; also UNDEF cannot have multiple values.
llvm-svn: 36622
2007-05-01 08:53:39 +00:00
Evan Cheng a684cd23a5 * Only turn a load to UNDEF if all of its outputs have no uses (indexed loads
produce two results.)
* Do not touch volatile loads.

llvm-svn: 36604
2007-05-01 00:38:21 +00:00
Christopher Lamb 8af6d5896f PR400 phase 2. Propagate attributed load/store information through DAGs.
llvm-svn: 36356
2007-04-22 23:15:30 +00:00
Reid Spencer 0c1349e6bc Revert Christopher Lamb's load/store alignment changes.
llvm-svn: 36309
2007-04-21 18:36:27 +00:00
Christopher Lamb bff50208c8 add support for alignment attributes on load/store instructions
llvm-svn: 36301
2007-04-21 08:16:25 +00:00
Chris Lattner f03c90bee6 allow SRL to simplify its operands, as it doesn't demand all bits as input.
llvm-svn: 36245
2007-04-18 03:06:49 +00:00
Chris Lattner bf14f20632 When replacing a node in SimplifyDemandedBits, if the old node used any
single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll

llvm-svn: 36244
2007-04-18 03:05:22 +00:00
Chris Lattner 9ad5915559 SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits
a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll

llvm-svn: 36212
2007-04-17 19:03:21 +00:00
Chris Lattner 18e4ac4107 fix an infinite loop compiling ldecod, notice by JeffC.
llvm-svn: 35910
2007-04-11 16:51:53 +00:00
Chris Lattner a083ffcad7 Fix this harder.
llvm-svn: 35888
2007-04-11 06:50:51 +00:00
Chris Lattner c5f85d3738 don't create shifts by zero, fix some problems with my previous patch
llvm-svn: 35887
2007-04-11 06:43:25 +00:00
Chris Lattner 65786b078c Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often
allows other simplifications.  For example, this compiles:
int isnegative(unsigned int X) {
   return !(X < 2147483648U);
}

Into this code:

x86:
        movl 4(%esp), %eax
        shrl $31, %eax
        ret
arm:
        mov r0, r0, lsr #31
        bx lr
thumb:
        lsr r0, r0, #31
        bx lr

instead of:

x86:
        cmpl $0, 4(%esp)
        sets %al
        movzbl %al, %eax
        ret

arm:
        mov r3, #0
        cmp r0, #0
        movlt r3, #1
        mov r0, r3
        bx lr

thumb:
        mov r2, #1
        mov r1, #0
        cmp r0, #0
        blt LBB1_2      @entry
LBB1_1: @entry
        cpy r2, r1
LBB1_2: @entry
        cpy r0, r2
        bx lr

Testcase here: test/CodeGen/Generic/ispositive.ll

llvm-svn: 35883
2007-04-11 05:32:27 +00:00
Chris Lattner 41189c63cc Codegen integer abs more efficiently using the trick from the PPC CWG. This
improves codegen on many architectures.  Tests committed as CodeGen/*/iabs.ll

X86 Old:			X86 New:
_test:				_test:
   movl 4(%esp), %ecx		   movl 4(%esp), %eax
   movl %ecx, %eax		   movl %eax, %ecx
   negl %eax			   sarl $31, %ecx
   testl %ecx, %ecx		   addl %ecx, %eax
   cmovns %ecx, %eax		   xorl %ecx, %eax
   ret				   ret

PPC Old:			PPC New:
_test:				_test:
   cmpwi cr0, r3, -1		   srawi r2, r3, 31
   neg r2, r3			   add r3, r3, r2
   bgt cr0, LBB1_2 ;		   xor r3, r3, r2
LBB1_1: ;			   blr
   mr r3, r2
LBB1_2: ;
   blr

ARM Old:			ARM New:
_test:				_test:
   rsb r3, r0, #0		   add r3, r0, r0, asr #31
   cmp r0, #0			   eor r0, r3, r0, asr #31
   movge r3, r0			   bx lr
   mov r0, r3
   bx lr

Thumb Old:			Thumb New:
_test:				_test:
   neg r2, r0			   asr r2, r0, #31
   cmp r0, #0			   add r0, r0, r2
   bge LBB1_2			   eor r0, r2
LBB1_1: @			   bx lr
   cpy r0, r2
LBB1_2: @
   bx lr


Sparc Old:			Sparc New:
test:				test:
   save -96, %o6, %o6		   save -96, %o6, %o6
   sethi 0, %l0			   sra %i0, 31, %l0
   sub %l0, %i0, %l0		   add %i0, %l0, %l1
   subcc %i0, -1, %l1		   xor %l1, %l0, %i0
   bg .BB1_2			   restore %g0, %g0, %g0
   nop				   retl
.BB1_1:				   nop
   or %g0, %l0, %i0
.BB1_2:
   restore %g0, %g0, %g0
   retl
   nop

It also helps alpha/ia64 :)

llvm-svn: 35881
2007-04-11 05:11:38 +00:00
Scott Michel 16627a542f 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605
2007-04-02 21:36:32 +00:00
Dale Johannesen 4bbd2eefba Fix incorrect combination of different loads. Reenable zext-over-truncate
combination.

llvm-svn: 35517
2007-03-30 21:38:07 +00:00
Evan Cheng ccee35fd0d Disable load width reduction xform of variant (zext (truncate load x)) for
big endian targets until llvm-gcc build issue has been resolved.

llvm-svn: 35449
2007-03-29 07:56:46 +00:00
Evan Cheng 8275f0e0af SIGN_EXTEND_INREG requires one extra operand, a ValueType node.
llvm-svn: 35350
2007-03-26 07:12:51 +00:00
Evan Cheng b7051f596a Adjust offset to compensate for big endian machines.
llvm-svn: 35293
2007-03-24 00:02:43 +00:00
Evan Cheng a883b58caf Make sure SEXTLOAD of the specific type is supported on the target.
llvm-svn: 35289
2007-03-23 22:13:36 +00:00
Evan Cheng e2f5f24e8e Also replace uses of SRL if that's also folded during ReduceLoadWidth().
llvm-svn: 35286
2007-03-23 20:55:21 +00:00
Evan Cheng a824e79f06 A couple of bug fixes for reducing load width xform:
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.

llvm-svn: 35274
2007-03-23 02:16:52 +00:00
Evan Cheng 464dc9b74c More opportunities to reduce load size.
llvm-svn: 35254
2007-03-22 01:54:19 +00:00
Evan Cheng d63baead9b fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))
llvm-svn: 35239
2007-03-21 20:14:05 +00:00
Evan Cheng 8a1d09d079 Avoid combining indexed load further.
llvm-svn: 35005
2007-03-07 08:07:03 +00:00
Chris Lattner 47206667c0 fold away addc nodes when we know there cannot be a carry-out.
llvm-svn: 34913
2007-03-04 20:40:38 +00:00
Chris Lattner 2dcc6e7f58 generalize
llvm-svn: 34910
2007-03-04 20:08:45 +00:00
Chris Lattner e2e13caeb2 canonicalize constants to the RHS of addc/adde. If nothing uses the carry out of
addc, turn it into add.

This allows us to compile:

long long test(long long A, unsigned B) {
  return (A + ((long long)B << 32)) & 123;
}

into:

_test:
        movl $123, %eax
        andl 4(%esp), %eax
        xorl %edx, %edx
        ret

instead of:
_test:
        xorl %edx, %edx
        movl %edx, %eax
        addl 4(%esp), %eax   ;; add of zero
        andl $123, %eax
        ret

llvm-svn: 34909
2007-03-04 20:03:15 +00:00
Chris Lattner fce448f856 Fold (sext (truncate x)) more aggressively, by avoiding creation of a
sextinreg if not needed.   This is useful in two cases: before legalize,
it avoids creating a sextinreg that will be trivially removed.  After legalize
if the target doesn't support sextinreg, the trunc/sext would not have been
removed before.

llvm-svn: 34621
2007-02-26 03:13:59 +00:00
Evan Cheng 92658d5648 Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer.
llvm-svn: 34065
2007-02-08 22:13:59 +00:00
Evan Cheng 00a640dbe0 Fix for PR1108: type of insert_vector_elt index operand is PtrVT, not MVT::i32.
llvm-svn: 33398
2007-01-20 10:10:26 +00:00
Evan Cheng 9201100b29 Remove this xform:
(shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
Replace it with:
(add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )

This fixes test/CodeGen/ARM/smul.ll

llvm-svn: 33361
2007-01-19 17:51:44 +00:00
Chris Lattner 4dc4489286 Fix PR1114 and CodeGen/Generic/2007-01-15-LoadSelectCycle.ll by being
careful when folding "c ? load p : load q" that C doesn't reach either load.
If so, folding this into load (c ? p : q) will induce a cycle in the graph.

llvm-svn: 33251
2007-01-16 05:59:59 +00:00
Chris Lattner f70c5cd5db add options to view the dags before the first or second pass of dag combine.
llvm-svn: 33249
2007-01-16 04:55:25 +00:00
Chris Lattner 0199fd6d59 Implement some trivial FP foldings when -enable-unsafe-fp-math is specified.
This implements CodeGen/PowerPC/unsafe-math.ll

llvm-svn: 33024
2007-01-08 23:04:05 +00:00
Chris Lattner aee775a6b7 Eliminate static ctors from Statistics
llvm-svn: 32698
2006-12-19 22:41:21 +00:00
Evan Cheng 28cf4277bb Cannot combine an indexed load / store any further.
llvm-svn: 32629
2006-12-16 06:25:23 +00:00
Jim Laskey 26df19ace6 This code was usurping the sextload expand in teh legalizer. Just make
sure the right conditions are checked.

llvm-svn: 32611
2006-12-15 21:38:30 +00:00
Chris Lattner b7524b6d0e make this code more aggressive about turning store fpimm into store int imm.
This is not sufficient to fix X86/store-fp-constant.ll

llvm-svn: 32465
2006-12-12 04:16:14 +00:00
Evan Cheng 218369881f Don't convert store double C, Ptr to store long C, Ptr if i64 is not a legal type.
llvm-svn: 32434
2006-12-11 17:25:19 +00:00
Nate Begeman 8e20c760fa Move something that should be in the dag combiner from the legalizer to the
dag combiner.

llvm-svn: 32431
2006-12-11 02:23:46 +00:00
Chris Lattner d9f04e4875 Fix CodeGen/PowerPC/2006-12-07-SelectCrash.ll on PPC64
llvm-svn: 32336
2006-12-07 22:36:47 +00:00
Bill Wendling 22e978a736 Removing even more <iostream> includes.
llvm-svn: 32320
2006-12-07 20:04:42 +00:00
Chris Lattner 700b873130 Detemplatize the Statistic class. The only type it is instantiated with
is 'unsigned'.

llvm-svn: 32279
2006-12-06 17:46:33 +00:00
Chris Lattner 3da631f29a For better or worse, load from i1 is assumed to be zero extended. Do not
form a load from i1 from larger loads that may not be zext'd.

llvm-svn: 31933
2006-11-27 04:40:53 +00:00
Chris Lattner 3676a994ca Fix PR1011 and CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
llvm-svn: 31878
2006-11-20 18:05:46 +00:00
Evan Cheng f64da389f8 Fix an incorrectly inverted condition.
llvm-svn: 31773
2006-11-16 00:08:20 +00:00
Chris Lattner a0a8003f59 disallow preinc of a frameindex. This is not profitable and causes 2-addr
pass to explode.  This fixes a bunch of llc-beta failures on ppc last night.

llvm-svn: 31661
2006-11-11 01:00:15 +00:00
Chris Lattner eabc15c1d8 reduce indentation by using early exits. No functionality change.
llvm-svn: 31660
2006-11-11 00:56:29 +00:00
Chris Lattner ffad2166e1 move big chunks of code out-of-line, no functionality change.
llvm-svn: 31658
2006-11-11 00:39:41 +00:00
Chris Lattner 4eac5f59e6 Fix a dag combiner bug exposed by my recent instcombine patch. This fixes
CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast

llvm-svn: 31644
2006-11-10 21:37:15 +00:00
Evan Cheng 13440b025c When forming a pre-indexed store, make sure ptr isn't the same or is a pred of value being stored. It would cause a cycle.
llvm-svn: 31631
2006-11-10 08:28:11 +00:00
Evan Cheng 6878378390 Don't attempt expensive pre-/post- indexed dag combine if target does not support them.
llvm-svn: 31598
2006-11-09 19:10:46 +00:00
Evan Cheng b15000736c Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
llvm-svn: 31595
2006-11-09 17:55:04 +00:00
Evan Cheng b58e06bc9e getPostIndexedAddressParts change: passes in load/store instead of its loaded / stored VT.
llvm-svn: 31584
2006-11-09 04:29:46 +00:00
Evan Cheng 85e54223cd Match more post-indexed ops.
llvm-svn: 31569
2006-11-08 20:27:27 +00:00
Jim Laskey 61feeb90f9 Remove redundant <cmath>.
llvm-svn: 31561
2006-11-08 19:16:44 +00:00
Evan Cheng 0303cb9b33 - When performing pre-/post- indexed load/store transformation, do not worry
about whether the new base ptr would be live below the load/store. Let two
  address pass split it back to non-indexed ops.
- Minor tweaks / fixes.

llvm-svn: 31544
2006-11-08 08:30:28 +00:00
Evan Cheng 6072435756 Fixed a minor bug preventing some pre-indexed load / store transformation.
llvm-svn: 31543
2006-11-08 06:56:05 +00:00
Evan Cheng d48f7dd250 Fix a obscure post-indexed load / store dag combine bug.
llvm-svn: 31537
2006-11-08 02:38:55 +00:00
Evan Cheng 60c6846d21 Add post-indexed load / store transformations.
llvm-svn: 31498
2006-11-07 09:03:05 +00:00
Evan Cheng eb99bd736a Add comment.
llvm-svn: 31473
2006-11-06 08:14:30 +00:00
Jeff Cohen 7d6f3db3e2 Unbreak VC++ build.
llvm-svn: 31464
2006-11-05 19:31:28 +00:00
Evan Cheng 33157700d9 Added pre-indexed store support.
llvm-svn: 31459
2006-11-05 09:31:14 +00:00
Evan Cheng 1dfd26a151 Rename
llvm-svn: 31413
2006-11-03 07:21:16 +00:00
Reid Spencer 52f958741a Remove dead variable. Fix 80 column violations.
llvm-svn: 31412
2006-11-03 03:30:34 +00:00
Evan Cheng 357017f4a9 Added DAG combiner transformation to generate pre-indexed loads.
llvm-svn: 31410
2006-11-03 03:06:21 +00:00
Reid Spencer de46e48420 For PR786:
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.

llvm-svn: 31380
2006-11-02 20:25:50 +00:00
Jim Laskey 55e4dcad36 Add option for controlling inclusion of global AA.
llvm-svn: 31040
2006-10-18 19:08:31 +00:00
Jim Laskey a15b0ebb5e Use global info for alias analysis.
llvm-svn: 31035
2006-10-18 12:29:57 +00:00
Chris Lattner 327b88b102 Fix CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
llvm-svn: 31019
2006-10-17 21:24:15 +00:00
Jim Laskey e7d2c24a7d Make it simplier to dump DAGs while in DAGCombiner. Remove a nasty optimization.
llvm-svn: 31009
2006-10-17 19:33:52 +00:00
Evan Cheng 1e3a39cd08 Make sure operand does have size and element type operands.
llvm-svn: 30999
2006-10-17 17:06:35 +00:00
Evan Cheng f3ae00a64a Be careful when looking through a vbit_convert. Optimizing this:
(vector_shuffle
  (vbitconvert (vbuildvector (copyfromreg v4f32), 1, v4f32), 4, f32),
  (undef, undef, undef, undef), (0, 0, 0, 0), 4, f32)
to the
  vbitconvert
is a very bad idea.

llvm-svn: 30989
2006-10-16 22:49:37 +00:00
Jim Laskey dcb2b83886 Pass AliasAnalysis thru to DAGCombiner.
llvm-svn: 30984
2006-10-16 20:52:31 +00:00