4 Commits

Author	SHA1	Message	Date
Nemanja Ivanovic	72d4866e57	[DAGCombiner] Expand combining of FP logical ops to sign-setting FP ops ... We already do the following combines: (bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X (bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X When the target has "bit preserving fp logic". This patch just extends it to also combine: (bitcast int (or (bitcast fp X to int), 0x8000...) to fp) -> fneg (fabs X) As some targets have fnabs and even those that don't can efficiently lower both the fabs and the fneg. Differential revision: https://reviews.llvm.org/D44548 llvm-svn: 344093	2018-10-09 23:20:11 +00:00
Sanjay Patel	a875030ab3	[AArch64][x86] add tests for bitcasted fnabs; NFC ... Alternate target coverage for D44548. llvm-svn: 344059	2018-10-09 17:20:26 +00:00
Sanjay Patel	e09b7dcf3d	[SelectionDAG] Removing FABS folding from DAGCombiner ... The code has bugs dealing with -0.0. Since D44550 introduced FABS pattern folding in InstCombine, this patch removes the now-redundant code that causes https://bugs.llvm.org/show_bug.cgi?id=36600. Patch by Mikhail Dvoretckii! Differential Revision: https://reviews.llvm.org/D44683 llvm-svn: 328872	2018-03-30 15:42:52 +00:00
Sanjay Patel	5a9210e651	[AArch64] add fabs tests for PR36600; NFC ... llvm-svn: 327995	2018-03-20 16:08:47 +00:00