71fcb4fedd
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
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Re-commit. This time complete with testsuite updates.
llvm-svn: 99570
2010-03-25 23:47:34 +00:00
42bb89c7d9
need to fix 'make check' tests first. revert for a moment.
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llvm-svn: 99569
2010-03-25 23:34:05 +00:00
7fce4e39aa
switch the flag for using NEON for SP floating point to a subtarget 'feature'
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llvm-svn: 99568
2010-03-25 23:32:19 +00:00
a3617ec88a
Removed instruction class NI from ARMInstrFormats.td.
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It doesn't seem to be used anywhere.
llvm-svn: 99566
2010-03-25 23:11:56 +00:00
a43386ba8f
switch the use-vml[as] instructions flag to a subtarget 'feature'
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llvm-svn: 99565
2010-03-25 23:11:16 +00:00
91d2774416
Add NVDupLnFrm and change NVDupLane class to use that format.
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llvm-svn: 99557
2010-03-25 21:49:12 +00:00
4b3b2ef65c
ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu
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llvm-svn: 99549
2010-03-25 20:48:50 +00:00
d82f9002e4
Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to
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expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.
llvm-svn: 99548
2010-03-25 20:39:04 +00:00
45ab3f3ccf
Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,
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instead of the current N2V. Format of NVDupLane instances are set to NEONFrm
currently.
llvm-svn: 99518
2010-03-25 17:01:27 +00:00
34de7768bf
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
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Preliminary testing shows significant performance wins by not using these
instructions.
llvm-svn: 99436
2010-03-24 22:31:46 +00:00
bff23ca690
Trivial formating change.
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llvm-svn: 99428
2010-03-24 21:25:07 +00:00
e99953ce9c
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
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NVCVTFrm will later be used to describe "vcvt with fractional bits".
llvm-svn: 99415
2010-03-24 19:47:14 +00:00
da44d5977f
Reverted r99376. The disassembler will deal with the 2-reg format of these two
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N3VX instructions using special case code.
llvm-svn: 99409
2010-03-24 18:46:34 +00:00
07607382d8
tweak the arm if conversion heuristic
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llvm-svn: 99402
2010-03-24 16:15:14 +00:00
aa9b1c81a7
Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
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llvm-svn: 99376
2010-03-24 01:29:25 +00:00
9b1f60adec
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
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respectively, and add some more comment.
llvm-svn: 99373
2010-03-24 00:57:50 +00:00
e0874fa02f
try being more permissive for if-conversion on ARM V7. see what the nightly
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test run permformance numbers say as to whether it helps.
llvm-svn: 99355
2010-03-24 00:03:13 +00:00
6a64320da8
Renamed NVdImmFrm to N1RegModImmFrm.
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llvm-svn: 99344
2010-03-23 23:09:14 +00:00
8a687233e3
Fix typo in the comment for N3VX class.
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llvm-svn: 99328
2010-03-23 21:35:03 +00:00
5be6d5a6a9
Add comment.
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llvm-svn: 99327
2010-03-23 21:30:12 +00:00
5dbf39285d
Add New NEON Format NVdVmVCVTFrm.
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Converted some of the NEON vcvt instructions to this format.
llvm-svn: 99326
2010-03-23 21:25:38 +00:00
020023a3fa
Add New NEON Format NVdVmImmFrm.
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llvm-svn: 99322
2010-03-23 20:40:44 +00:00
59f75bba24
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
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These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
llvm-svn: 99309
2010-03-23 18:54:46 +00:00
3968c6a252
Fix bad indentation, 80-column violations, and trailing whitespace.
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llvm-svn: 99295
2010-03-23 17:23:59 +00:00
ac5024bbeb
Add New NEON Format NVdImmFrm.
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Ref: A7.4.6 One register and a modified immediate value.
llvm-svn: 99288
2010-03-23 16:43:47 +00:00
9b680e21c0
Rename some instructions to match the corresponding NEON opcode.
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llvm-svn: 99266
2010-03-23 06:26:18 +00:00
cc0a2a75a0
Change VST1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
llvm-svn: 99265
2010-03-23 06:20:33 +00:00
340861d29e
Change VLD1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
llvm-svn: 99261
2010-03-23 05:25:43 +00:00
e60e3ab624
Rename one more NEON instruction that I missed earlier.
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llvm-svn: 99201
2010-03-22 20:31:39 +00:00
c286c88db0
Regroup some instructions. No functional change.
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llvm-svn: 99192
2010-03-22 18:22:06 +00:00
c53a1125ff
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
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corresponding NEON instructions, instead of operation they are currently
used for.
llvm-svn: 99189
2010-03-22 18:13:18 +00:00
98bf5189d7
Remove some redundant instruction classes.
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llvm-svn: 99187
2010-03-22 18:02:38 +00:00
debe0bdb13
Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
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specify encoding bits in arguments instead of "let" expressions.
llvm-svn: 99185
2010-03-22 16:43:10 +00:00
7d116ce2e3
Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters.
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llvm-svn: 99182
2010-03-22 16:13:21 +00:00
fed917e078
TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.
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llvm-svn: 99097
2010-03-20 22:36:22 +00:00
162242b63b
pr6652: Use LDM to restore PC to the return address on ARMv4.
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Patch by John Tytgat!
llvm-svn: 99096
2010-03-20 22:20:40 +00:00
ae08a736d6
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
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with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
llvm-svn: 99095
2010-03-20 22:13:40 +00:00
59e5141d44
Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with
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address register writeback.
llvm-svn: 99094
2010-03-20 21:57:36 +00:00
b18adef4ad
Add variants of VST2, VST3 and VST4 with address register writeback, and
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rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.
llvm-svn: 99093
2010-03-20 21:45:18 +00:00
89ba42c4ce
Add instructions for double-spaced VST3 and VST4 without address register
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writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
llvm-svn: 99090
2010-03-20 21:15:48 +00:00
322cbff3d3
Add VST1 instructions with address register writeback.
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llvm-svn: 99083
2010-03-20 20:54:36 +00:00
9152d96dfb
Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with
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address register writeback.
llvm-svn: 99082
2010-03-20 20:47:18 +00:00
9b1584245a
Tidy some more comments and whitespace.
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llvm-svn: 99081
2010-03-20 20:39:53 +00:00
cf324658f6
Add variants of VLD2, VLD3 and VLD4 with address register writeback, and
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rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.
llvm-svn: 99080
2010-03-20 20:10:51 +00:00
7ee900da22
Tidy some comments and whitespace for consistency.
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llvm-svn: 99078
2010-03-20 19:57:03 +00:00
c0795f8b87
Rename some instructions for consistency and sanity: use "_UPD" suffix for
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load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.
llvm-svn: 99066
2010-03-20 18:35:24 +00:00
d092669b48
Add instructions for double-spaced VLD3 and VLD4 without address register
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writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
llvm-svn: 99065
2010-03-20 18:14:26 +00:00
496766cb56
Add VLD1 instructions with address register writeback.
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llvm-svn: 99062
2010-03-20 17:59:03 +00:00
2497d85c9e
Revert the rest of 98679.
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--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U lib/Target/ARM/ARMInstrVFP.td
llvm-svn: 99049
2010-03-20 06:34:02 +00:00
614d1fdfc3
Fix a very bad typo. Since the register number was off by one, the ARM
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load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.
llvm-svn: 99043
2010-03-20 06:05:13 +00:00
Jim Grosbach