9d0136274b
Direct calls only for arm fast isel for now.
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llvm-svn: 115350
2010-10-01 21:33:12 +00:00
2a5d764858
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
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llvm-svn: 115344
2010-10-01 20:50:58 +00:00
6080da7a79
Fix thinko on store instructions. Fixes test_indvars failure.
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llvm-svn: 115342
2010-10-01 20:46:04 +00:00
2ecba4a07e
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.
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llvm-svn: 115341
2010-10-01 20:33:47 +00:00
671d57865e
Provide an option to restore old-style if-conversion heuristics for Thumb2.
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llvm-svn: 115339
2010-10-01 20:28:06 +00:00
89e6f6759f
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.
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llvm-svn: 115332
2010-10-01 19:41:46 +00:00
05ed521a88
grammar
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llvm-svn: 115314
2010-10-01 14:57:48 +00:00
c1e209d40e
Implement double return values in calls. Fixes
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SingleSource/Regression/C/casts.c.
llvm-svn: 115246
2010-10-01 00:00:11 +00:00
b9b63ee031
Temporarily add a flag to make it easier to compare the new-style ARM if
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conversion heuristics to the old-style ones.
llvm-svn: 115239
2010-09-30 23:48:38 +00:00
56094ff402
Movement and cleanup.
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llvm-svn: 115225
2010-09-30 22:34:19 +00:00
78f8d4eaf0
Start of generalized call support for ARM fast isel.
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llvm-svn: 115203
2010-09-30 20:49:44 +00:00
c8e2e9d830
Nuke a few more unused asm strings
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llvm-svn: 115193
2010-09-30 19:53:58 +00:00
7e872969ce
Move getPointerSize() to the base class since it's not dependent on MachO
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vs. ELF
llvm-svn: 115180
2010-09-30 17:45:51 +00:00
5a5ddc402e
Remove extraneous ';'
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llvm-svn: 115176
2010-09-30 17:19:17 +00:00
b9429179f9
The asm strings are never used at all, so just nuke 'em entirely.
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llvm-svn: 115160
2010-09-30 16:56:53 +00:00
bad267fa05
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
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for the dwarf .loc support to emit dwarf line number tables.
llvm-svn: 115153
2010-09-30 16:38:07 +00:00
136ed51b08
80 column fix
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llvm-svn: 115149
2010-09-30 15:25:22 +00:00
6c233c141e
Fix two tiny issues (ARM does not need COFF) and comment sanity.
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llvm-svn: 115147
2010-09-30 14:58:19 +00:00
689651c767
trailing whitespace
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llvm-svn: 115136
2010-09-30 03:21:00 +00:00
58bce99385
Remove misplaced ';'. Make buildbots happy, hopefully.
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llvm-svn: 115135
2010-09-30 03:20:34 +00:00
645f6c2bef
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
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Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
llvm-svn: 115133
2010-09-30 02:45:56 +00:00
4a9cb8f10e
Go ahead and jump!
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Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
2010-09-30 02:18:06 +00:00
b32124545b
I added a new file ARMAsmBackend which stubs out in similar ways to
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the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)
Tested against -r115126
llvm-svn: 115129
2010-09-30 02:17:26 +00:00
2ff7de0264
Now that the pseudos that needed this are all custom lowered, we can go back
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to an empty PrintSpecial()
llvm-svn: 115128
2010-09-30 02:02:22 +00:00
080fdf4609
Nuke it from orbit. It's the only way to be sure.
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(Kill the dead non-MC asm printer for the ARM target.)
llvm-svn: 115127
2010-09-30 01:57:53 +00:00
2fb20b1d37
ARM instruction itinerary fixes:
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1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
7939806ecc
Refactor arm fast isel libcall handling so that pieces can be used
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for generic call handling.
llvm-svn: 115105
2010-09-29 23:11:09 +00:00
4a010fd1ea
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
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pipeline forwarding path.
llvm-svn: 115098
2010-09-29 22:42:35 +00:00
b024be3162
Add a convenience variable so I'm not chasing all over looking for
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a context.
llvm-svn: 115094
2010-09-29 22:24:45 +00:00
0860520527
Add specializations of addrmode2 that allow differentiating those forms
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which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.
llvm-svn: 115066
2010-09-29 19:03:54 +00:00
97bf273870
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
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LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
llvm-svn: 115047
2010-09-29 17:54:10 +00:00
c7b10f3745
Add braces for legibility.
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llvm-svn: 115043
2010-09-29 17:32:29 +00:00
05eccf0e44
One Printer to rule them all, One Printer to find them,
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One Printer to lower them all and in the back end bind them.
(Remove option to use the old non-MC asm printer.)
llvm-svn: 115038
2010-09-29 15:23:40 +00:00
d36e3e8850
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
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added some doxygen on the way
llvm-svn: 115033
2010-09-29 10:12:08 +00:00
a63292a3ca
implement rdar://8456378 and PR7557 - support for the fstsw,
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an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
b44fd24fc1
change the protocol TargetAsmPArser::MatchInstruction method to take an
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MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
llvm-svn: 115014
2010-09-29 01:42:58 +00:00
3a7e8cd6bd
Rework comparison handling to set a register on true/false. This avoids
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problems with phi-nodes in blocks that have hard and not virtual registers.
Accordingly update branch handling to compensate.
llvm-svn: 115013
2010-09-29 01:14:47 +00:00
edd4b600f3
Remove unnecessary set ahead of time.
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llvm-svn: 115011
2010-09-29 00:50:57 +00:00
2259d67a33
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
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llvm-svn: 115010
2010-09-29 00:49:25 +00:00
2c8e7f421c
Remove assert, add comment.
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llvm-svn: 115009
2010-09-29 00:49:09 +00:00
c35d7bbe43
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
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llvm-svn: 115008
2010-09-29 00:27:46 +00:00
0097dd0d5a
Add support to model pipeline bypass / forwarding.
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llvm-svn: 115005
2010-09-28 23:50:49 +00:00
a86a6d2fed
32-bit constant ints only for now.
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llvm-svn: 115001
2010-09-28 22:47:54 +00:00
b4b12535e8
Removed a bunch of unnecessary target_link_libraries.
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llvm-svn: 114999
2010-09-28 22:39:14 +00:00
a3181e2d79
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
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cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
llvm-svn: 114995
2010-09-28 21:57:50 +00:00
953b1afd5f
Integer materialization needed the same thinko change.
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llvm-svn: 114994
2010-09-28 21:55:34 +00:00
7d483d352b
Resolve this GCC warning:
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ARMTargetMachine.cpp:53: error: control reaches end of non-void function
llvm-svn: 114992
2010-09-28 21:40:26 +00:00
81bdc93bbb
User proper libcall names & condcodes while compiling for ARM EABI.
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Patch by Evzen Muller!
llvm-svn: 114991
2010-09-28 21:39:26 +00:00
88af7d00fc
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
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Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
llvm-svn: 114973
2010-09-28 18:32:13 +00:00
45c83d496f
Factor out dbg_value comment printing and teach MC asm printing to use it.
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This should make the arm-linux self-host buildbot happy again.
llvm-svn: 114964
2010-09-28 17:05:56 +00:00
Eric Christopher