e5f4a6d904
Increase the initial vector size to be equivalent to the size of the Deps
...
vector. This potentially saves a resizing.
llvm-svn: 149369
2012-01-31 07:04:52 +00:00
8a33312948
Cache the size of the vector instead of calling .size() all over the place.
...
llvm-svn: 149368
2012-01-31 06:57:53 +00:00
b85e40f738
Remove pcmpgt/pcmpeq intrinsics as clang is not using them.
...
llvm-svn: 149367
2012-01-31 06:52:44 +00:00
f1179025ae
eliminate the "string" form of ConstantArray::get, using
...
ConstantDataArray::getString instead.
llvm-svn: 149365
2012-01-31 06:18:43 +00:00
8ea967d050
with recent changes, ConstantArray is never a "string". Remove the associated
...
methods and constant fold the clients to false.
llvm-svn: 149362
2012-01-31 06:05:00 +00:00
2b3c187489
RAFast: Generalize the logic for return operands.
...
This removes implicit assumption about the form of MI coming into regalloc. In particular, it should be independent of ProcessImplicitDefs which will eventually become a standard part of coming out of SSA--unless we simply can eliminate IMPLICIT_DEF completely. Current unit tests expose this once I remove incidental pass ordering restrictions.
This is not a final fix. Just a temporary workaround until I figure out the right way.
llvm-svn: 149360
2012-01-31 05:55:32 +00:00
06d673678e
fix a small oversight that broke the fhourstones app.
...
llvm-svn: 149357
2012-01-31 05:18:56 +00:00
997348e9fe
remove the last vestiges of llvm::GetConstantStringInfo, in CodeGen.
...
llvm-svn: 149356
2012-01-31 05:09:17 +00:00
9e4b8726f8
eliminate the last uses of GetConstantStringInfo from this file, I didn't realize I was that close...
...
llvm-svn: 149354
2012-01-31 04:54:27 +00:00
b90c102a52
Add various coarse bit-width architecture predicates to llvm::Triple.
...
These are very useful for frontends and other utilities reasoning about
or selecting between triples.
llvm-svn: 149353
2012-01-31 04:52:32 +00:00
8193b06e44
start moving SimplifyLibcalls over to getConstantStringInfo, which is
...
dramatically more efficient than GetConstantStringInfo.
llvm-svn: 149352
2012-01-31 04:43:11 +00:00
108423a94a
Change ConstantArray::get to form a ConstantDataArray when possible,
...
kicking in the big win of ConstantDataArray. As part of this, change
the implementation of GetConstantStringInfo in ValueTracking to work
with ConstantDataArray (and not ConstantArray) making it dramatically,
amazingly, more efficient in the process and renaming it to
getConstantStringInfo.
This keeps around a GetConstantStringInfo entrypoint that (grossly)
forwards to getConstantStringInfo and constructs the std::string
required, but existing clients should move over to
getConstantStringInfo instead.
llvm-svn: 149351
2012-01-31 04:42:22 +00:00
983005f51b
rework this logic to not depend on the last argument to GetConstantStringInfo,
...
which is going away.
llvm-svn: 149348
2012-01-31 04:39:22 +00:00
0d3785e165
don't emit a 1-byte object as a .fill. This is silly and causes
...
CodeGen/X86/global-sections.ll to fail with CDArray
llvm-svn: 149343
2012-01-31 03:39:24 +00:00
3a565d6241
use the right accessor for ConstantDataArray.
...
llvm-svn: 149342
2012-01-31 03:16:39 +00:00
9c181f660c
fix asmwriting of ConstantDataArray to use the right element count,
...
simplify ConstantArray handling, since they can never be empty.
llvm-svn: 149341
2012-01-31 03:15:40 +00:00
fe741769dd
enhance logic to support ConstantDataArray.
...
llvm-svn: 149340
2012-01-31 02:55:06 +00:00
8d9d1a0022
Remove the now-dead llvm.eh.exception and llvm.eh.selector intrinsics.
...
llvm-svn: 149331
2012-01-31 01:58:48 +00:00
3fd879dde2
s/getInnerUnwindDest/getInnerResumeDest/g
...
llvm-svn: 149328
2012-01-31 01:48:40 +00:00
a4237652d2
Remove the eh.exception and eh.selector intrinsics. Also remove a hack to copy
...
over the catch information. The catch information is now tacked to the invoke
instruction.
llvm-svn: 149326
2012-01-31 01:46:13 +00:00
ea6e935e95
Remove ivar which is identical to another ivar.
...
llvm-svn: 149323
2012-01-31 01:25:54 +00:00
0c2d82b942
Remove unused ivars and s/getOuterUnwindDest/getOuterResumeDest/g.
...
llvm-svn: 149322
2012-01-31 01:22:03 +00:00
7778e6d818
Remove more dead functions.
...
llvm-svn: 149318
2012-01-31 01:18:21 +00:00
803d6b1b0c
s/getInnerUnwindDestNewEH/getInnerUnwindDest/g
...
llvm-svn: 149317
2012-01-31 01:15:59 +00:00
621699de22
Remove some unused, old-EH methods.
...
llvm-svn: 149316
2012-01-31 01:14:49 +00:00
18a4c31525
Use the correct ShiftAmtTy for creating shifts after legalization. PR11881. Not committing a testcase because I think it will be too fragile.
...
llvm-svn: 149315
2012-01-31 01:08:03 +00:00
518a205d0a
Get rid of references to dead intrinsics.
...
The eh.selector and eh.resume intrinsics aren't used anymore. Get rid of some
calls to them.
llvm-svn: 149314
2012-01-31 01:05:20 +00:00
ce0c229234
Formatting cleanups. No functionality change.
...
llvm-svn: 149312
2012-01-31 01:01:16 +00:00
f3cae51490
Remove no-longer-useful dyn_casts and pals.
...
llvm-svn: 149307
2012-01-31 00:56:53 +00:00
bd7ed6fe7c
Add a constified getLandingPad() method.
...
llvm-svn: 149303
2012-01-31 00:26:24 +00:00
22ddcfd2df
[asan] fix the ObjC support (asan Issue #33 )
...
llvm-svn: 149300
2012-01-30 23:50:10 +00:00
2c469ff14a
Chris's constant data sequence refactoring actually enabled printing
...
vectors of all one bits to be printed more cleverly in the AsmPrinter.
Unfortunately, the byte value for all one bits is the same with
-fsigned-char as the error return of '-1'. Force this to be the unsigned
byte value when returning it to avoid this problem, and update the test
case for the shiny new behavior.
Yay for building LLVM and Clang with -funsigned-char.
Chris, please review, and let me know if there is any reason to not
desire this change. It seems good on the surface, and certainly intended
based on the code written.
llvm-svn: 149299
2012-01-30 23:47:44 +00:00
4e7992eeba
PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina.
...
llvm-svn: 149294
2012-01-30 23:10:32 +00:00
7cdb2ff6b5
Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
...
llvm-svn: 149291
2012-01-30 22:47:12 +00:00
6a0baa8f09
Typo.
...
llvm-svn: 149289
2012-01-30 22:44:13 +00:00
41003f819c
Typo.
...
llvm-svn: 149275
2012-01-30 21:13:22 +00:00
6291f3a43c
Implement String Cast from Integer
...
Allow casts from integer to string.
llvm-svn: 149273
2012-01-30 20:47:04 +00:00
9a9bb5c5db
Intel syntax. Support .intel_syntax directive.
...
llvm-svn: 149270
2012-01-30 20:02:42 +00:00
396c590818
Fix refacto.
...
llvm-svn: 149269
2012-01-30 20:01:35 +00:00
9cc6d524ea
Here's a new one: GCC was complaining about an only-used-in-asserts
...
*function*. Wrap the function in #ifndef NDEBUG.
llvm-svn: 149259
2012-01-30 19:26:20 +00:00
f06039b39d
Various improvements suggested by Duncan
...
llvm-svn: 149255
2012-01-30 18:19:30 +00:00
e577cfe172
Eliminate narrowing conversion in initializer list, to make C++11 happy
...
llvm-svn: 149254
2012-01-30 16:57:18 +00:00
20af25f47b
X86: Simplify shuffle mask generation code.
...
llvm-svn: 149248
2012-01-30 15:16:21 +00:00
7a36f9d399
Fix compilation of ASan tests on OS X Lion (see http://code.google.com/p/address-sanitizer/issues/detail?id=32 )
...
The redzones emitted by AddressSanitizer for CFString instances confuse the linker and are of little use, so we shouldn't add them.
llvm-svn: 149243
2012-01-30 10:40:22 +00:00
516cba3380
Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary.
...
llvm-svn: 149232
2012-01-30 07:50:31 +00:00
5d917075fd
fix a major oversight that is breaking some llvm-test tests.
...
llvm-svn: 149230
2012-01-30 07:36:01 +00:00
978fe0c75a
First step of flipping on ConstantDataSequential: enable ConstantDataVector
...
to be formed whenever ConstantVector::get is used.
llvm-svn: 149226
2012-01-30 06:21:21 +00:00
829400bb22
when verbose asm is on, print integers in ConstantDataSequentials just
...
like normal integers.
llvm-svn: 149223
2012-01-30 05:55:11 +00:00
51ebe14a36
don't lose tail padding on ConstantDataAggregate vec3's.
...
llvm-svn: 149222
2012-01-30 05:49:43 +00:00
c2783009b3
Fix ConstantFoldShuffleVectorInstruction to properly handle the case
...
when the result type has a different # elements than the input vectors.
llvm-svn: 149221
2012-01-30 05:34:13 +00:00
ca29bcfc10
Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
...
llvm-svn: 149216
2012-01-30 01:10:15 +00:00
372dd1ea18
Add bitcode reader and writer support for ConstantDataAggregate, which
...
should be feature complete now. Lets see if it works.
llvm-svn: 149215
2012-01-30 00:51:16 +00:00
7039e358fc
Move Clang's file-level locking facility over to LLVM's support
...
library, since it doesn't really have anything to do with Clang.
llvm-svn: 149203
2012-01-29 20:15:10 +00:00
d0c46550fe
Cleanups for EABI standard functions
...
llvm-svn: 149195
2012-01-29 09:11:50 +00:00
1b42e64280
Use base AAPCS for varargs functions even for AAPCS-VFP CC
...
llvm-svn: 149194
2012-01-29 09:06:09 +00:00
198236edae
Fix some scavenger performance issues.
...
- Don't call malloc+free in the very hot forward().
- Don't call isTiedToDefOperand().
- Don't create BitVector temporaries.
- Merge DeadRegs into KillRegs.
- Eliminate the early clobber checks, they were irrelevant to scavenging.
- Remove unnecessary code from -Asserts builds.
This speeds up ARM PEI by 3.4x and overall llc -O0 codegen time by 11%.
llvm-svn: 149189
2012-01-29 01:29:28 +00:00
8b1853ddef
Avoid creating BitVector temporaries.
...
llvm-svn: 149188
2012-01-29 01:29:25 +00:00
1b3167edec
Fix typo.
...
llvm-svn: 149185
2012-01-28 23:33:44 +00:00
de0c335560
Add a note about a potential optimization for clz/ctz patterns for ARM
...
(and other targets).
llvm-svn: 149182
2012-01-28 18:30:07 +00:00
b47489d4ef
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
...
Fixes PR11877
llvm-svn: 149180
2012-01-28 15:58:32 +00:00
4efe5064c3
Silence GCC's -Wreturn-type warning.
...
llvm-svn: 149179
2012-01-28 15:28:41 +00:00
004725876e
Small improvement to the recursion detection logic from the previous commit.
...
llvm-svn: 149175
2012-01-28 06:22:14 +00:00
72f5f170c6
Handle recursive variable definitions directly. This gives us better error
...
messages and allows us to fix PR11865.
llvm-svn: 149174
2012-01-28 05:57:00 +00:00
7471d1303d
[asan] correctly use ConstantExpr::getGetElementPtr. Catch by NAKAMURA Takumi
...
llvm-svn: 149172
2012-01-28 04:27:16 +00:00
8c09040854
Reapply r149159 with a fix to add to a PHI node with a non-null parent.
...
llvm-svn: 149164
2012-01-28 01:17:56 +00:00
d78ec25e65
Remove code that adds live ranges for dead defs. It seems to be breaking things.
...
llvm-svn: 149163
2012-01-28 01:17:01 +00:00
fa5ad212f8
Revert r149159 until I can fix tests.
...
llvm-svn: 149162
2012-01-28 01:10:01 +00:00
b4544544a6
Don't always create a separate block for the call to _Unwind_Resume.
...
Sometimes there is only one 'resume' instruction per function. In those
situations, we don't need a separate block for the call to _Unwind_Resume. In
fact, it adds a lot of overhead to code-gen if we do that -- especially at -O0.
If we have a single 'resume' instruction, just generate the call within that
block.
<rdar://problem/10694814>
llvm-svn: 149159
2012-01-28 00:47:18 +00:00
ebb006fc3d
Fix Record Name Reference
...
Get the record name though the init to avoid an assert.
llvm-svn: 149153
2012-01-28 00:03:24 +00:00
a6958c6c4e
Silence warning about parens for && within ||
...
llvm-svn: 149152
2012-01-27 23:52:25 +00:00
bb893fea6b
Add r149110 back with a fix for when the vector and the int have the same
...
width.
llvm-svn: 149151
2012-01-27 23:33:07 +00:00
a4062624d1
Revert r149110 and add a testcase that was crashing since that revision.
...
Unfortunately I also had to disable constant-pool-sharing.ll the code it tests has been
updated to use the IL logic.
llvm-svn: 149148
2012-01-27 22:42:48 +00:00
ad33d5ace7
Add a "moveInstr" method to LiveIntervals. This can be used to move instructions
...
around within a basic block while maintaining live-intervals.
Updated ScheduleTopDownLive in MachineScheduler.cpp to use the moveInstr API
when reordering MIs.
llvm-svn: 149147
2012-01-27 22:36:19 +00:00
6f108d9229
Backing out ill-considered 'refactor'.
...
llvm-svn: 149146
2012-01-27 21:43:32 +00:00
376a2d3e99
Move some duplicate loops in the coalescer into their own function.
...
llvm-svn: 149144
2012-01-27 19:58:14 +00:00
63fe5697f4
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
...
llvm-svn: 149142
2012-01-27 19:48:28 +00:00
5639e9e8fb
Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition.
...
llvm-svn: 149122
2012-01-27 07:09:40 +00:00
9e18b6672a
Physreg dead defs should be handled too.
...
llvm-svn: 149118
2012-01-27 03:20:42 +00:00
cc3aaf1836
smallvectorize.
...
llvm-svn: 149117
2012-01-27 03:15:49 +00:00
0256be96f2
continue making the world safe for ConstantDataVector. At this point,
...
we should (theoretically optimize and codegen ConstantDataVector as well
as ConstantVector.
llvm-svn: 149116
2012-01-27 03:08:05 +00:00
7717e9f4ae
Place the GEP instructions nearer to the instructions which use them.
...
GEP instructions are there for the compiler and shouldn't really output much
code (if any at all). When a GEP is stored in the entry block, Fast ISel (for
one) will not know that it could fold it into further uses. For instance, inside
of the EH handling code. This results in a lot of unnecessary spills and loads
which bloat code and slows down pretty much everything.
<rdar://problem/10694814>
llvm-svn: 149114
2012-01-27 02:02:24 +00:00
e32fad43b1
make sure the file's matching header is #include'd first.
...
llvm-svn: 149113
2012-01-27 01:47:28 +00:00
7ba81830ff
Rewrite CanShareConstantPoolEntry to be implemented in terms of the
...
mid-level constant folding APIs instead of doing its own analysis.
This makes it more general (e.g. can now share a <2 x i64> with a
<4 x i32>) and avoid duplicating a bunch of logic.
llvm-svn: 149111
2012-01-27 01:46:00 +00:00
111d6ee655
enhance constant folding to be able to constant fold bitcast of
...
ConstantVector's to integer type.
llvm-svn: 149110
2012-01-27 01:44:03 +00:00
8f28dbdde5
Keep source location information for X86 MCFixup's.
...
llvm-svn: 149106
2012-01-27 00:51:27 +00:00
d856fd0d99
Source information in 'expected relocatable expression' diagnostic.
...
llvm-svn: 149105
2012-01-27 00:51:23 +00:00
20275a8577
Better user diagnostics for more ARM MachO relocation errors.
...
llvm-svn: 149102
2012-01-27 00:37:12 +00:00
b591277c4a
Better diagnostic for malformed .org assembly directive.
...
Provide source line number information.
llvm-svn: 149101
2012-01-27 00:37:08 +00:00
286fed5c8c
Rewrite instruction operands in AdjustCopiesBackFrom. Fixes PR11861.
...
llvm-svn: 149097
2012-01-27 00:05:42 +00:00
5aac954be9
Tidy up.
...
llvm-svn: 149096
2012-01-26 23:47:45 +00:00
5e5eabb5ab
Keep source information, if available, around for ARM Fixups.
...
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.
Before:
LLVM ERROR: unknown ARM fixup kind!
After:
x.s:6:5: error: unsupported relocation on symbol
beq bar
^
rdar://9800182
llvm-svn: 149093
2012-01-26 23:20:15 +00:00
b18b409258
Add simple support for keeping MCFixup source information.
...
Can be used to issue more user friendly diagnostics for faulty
relocation constructs and such.
llvm-svn: 149092
2012-01-26 23:20:11 +00:00
dfc5b555da
Add SourceMgr to MCContext for backend diagnostics.
...
llvm-svn: 149090
2012-01-26 23:20:05 +00:00
fc9dce25f7
Handle call-clobbered ymm registers on Win64.
...
The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.
Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered. This allows live xmm
registers across calls.
This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.
llvm-svn: 149088
2012-01-26 22:59:28 +00:00
61a1d6cb81
progress making the world safe to ConstantDataVector. While
...
we're at it, allow PatternMatch's "neg" pattern to match integer
vector negations, and enhance ComputeNumSigned bits to handle
shl of vectors.
llvm-svn: 149082
2012-01-26 21:37:55 +00:00
88fce10928
tidy up forward declarations.
...
llvm-svn: 149078
2012-01-26 20:44:57 +00:00
a474bb265b
smallvectorize and ArrayRef'ize some stuff.
...
llvm-svn: 149077
2012-01-26 20:40:56 +00:00
37e3835a94
Reduce a lot of code duplication by implementing
...
ConstantExpr::getWithOperandReplaced and ConstantExpr::replaceUsesOfWithOnConstant
in terms of ConstantExpr::getWithOperands. While we're at it,
make sure that ConstantExpr::getWithOperands covers all instructions: it was
missing insert/extractvalue.
llvm-svn: 149076
2012-01-26 20:37:11 +00:00
9b61cf3167
Update comment for r149070.
...
llvm-svn: 149075
2012-01-26 20:19:05 +00:00
1a1531d65e
Replace the use of isPredicable() with isPredicated() in
...
MachineBasicBlock::canFallThrough(). We're interested in the state of the
instruction (i.e., is this a barrier or not?), not if the instruction is
predicable or not.
rdar://10501092
llvm-svn: 149070
2012-01-26 18:24:25 +00:00
8c139a5125
Clear kill flags before propagating a copy.
...
The live range of the source register may be extended when a redundant
copy is eliminated. Make sure any kill flags between the two copies are
cleared.
This fixes PR11765.
llvm-svn: 149069
2012-01-26 17:52:15 +00:00
c8f2b7877b
Tidy up. Fix mismatched return types for error handling.
...
llvm-svn: 149062
2012-01-26 15:56:45 +00:00
6685c08e5f
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
...
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
llvm-svn: 149057
2012-01-26 09:25:43 +00:00
5f29b0e57b
Fix for the following bug in AVX codegen for double-to-int conversions:
...
. "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
. Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
. Consequently, the conversion produces incorrect numbers.
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode.
As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec).
llvm-svn: 149056
2012-01-26 08:51:39 +00:00
86e44bc829
Add HasXOP predicate check covering a bunch of XOP intrinsic patterns.
...
llvm-svn: 149054
2012-01-26 07:51:55 +00:00
1c0e22f57a
Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM.
...
llvm-svn: 149053
2012-01-26 07:31:30 +00:00
b91760eff8
Remove some more patterns by custom lowering intrinsics to target specific nodes.
...
llvm-svn: 149052
2012-01-26 07:18:03 +00:00
34d9a17778
unbreak test/Bitcode/shuffle.ll.
...
llvm-svn: 149033
2012-01-26 03:10:45 +00:00
8722fe5a24
simplify by using ShuffleVectorInst::getMaskValue.
...
llvm-svn: 149029
2012-01-26 02:54:54 +00:00
cf12970bd0
eliminate the Constant::getVectorElements method. There are better (and
...
more robust) ways to do what it was doing now. Also, add static methods
for decoding a ShuffleVector mask.
llvm-svn: 149028
2012-01-26 02:51:13 +00:00
fa77500d96
Continue improving support for ConstantDataAggregate, and use the
...
new methods recently added to (sometimes greatly!) simplify code.
llvm-svn: 149024
2012-01-26 02:32:04 +00:00
f14a67f5d3
Add a ConstantDataVector::getSplatValue() method, for parity with
...
ConstantVector. Fix some outright bugs in the implementation of
ConstantArray and Constant struct, which would cause us to not make
one big UndefValue when asking for an array/struct with all undef
elements. Enhance Constant::isAllOnesValue to work with
ConstantDataVector.
llvm-svn: 149021
2012-01-26 02:31:22 +00:00
8326bd8e10
some general cleanup, using new methods and tidying up old code.
...
llvm-svn: 149006
2012-01-26 00:42:34 +00:00
3dbad40341
fix pasto in the new (and still unused) ShuffleVectorInst::getShuffleMask method.
...
llvm-svn: 149005
2012-01-26 00:41:50 +00:00
154aabc0c4
add StructType helpers too.
...
llvm-svn: 149000
2012-01-26 00:06:44 +00:00
40a279e1c5
Ok, break down and add some cast<>'ing helper methods to the Type class
...
to reduce the number of cast<>'s we have. This allows someone to use
things like Ty->getVectorNumElements() instead of
cast<VectorType>(Ty)->getNumElements() when you know that a type is a
vector.
It would be a great general cleanup to move the codebase to use these,
I will do so in the code I'm touching.
llvm-svn: 148999
2012-01-26 00:01:10 +00:00
1dcb654311
add some helper methods to ShuffleVectorInst and enhance its
...
"isValidOperands" and "getMaskValue" methods to allow
ConstantDataSequential.
llvm-svn: 148998
2012-01-25 23:49:49 +00:00
4864a81aa3
Improve sub-register def handling in ProcessImplicitDefs.
...
This boils down to using MachineOperand::readsReg() more.
This fixes PR11829 where a use ended up after the first def when
lowering REG_SEQUENCE instructions involving IMPLICIT_DEFs.
llvm-svn: 148996
2012-01-25 23:36:27 +00:00
7722a2d4e3
Properly emit ctors / dtors with priorities into desired sections
...
and let linker handle the rest.
This finally fixes PR5329
llvm-svn: 148990
2012-01-25 22:24:19 +00:00
f1508b78f9
Don't add live ranges for aliases of physregs that are live in to the
...
function. They don't appear to be used, and are inconsistent with handling of
other physreg intervals (i.e. intervals that are not live-in) where ranges are
not inserted for aliases.
llvm-svn: 148986
2012-01-25 22:11:06 +00:00
65e2465550
Tidy up. s/Low Level Virtual Machine/LLVM/.
...
LLVM isn't an acronym anymore.
llvm-svn: 148985
2012-01-25 22:00:23 +00:00
19feb5f241
Always break upon finding a vreg operand (in Release as well as +Asserts). Remove assertion which can no longer trigger.
...
llvm-svn: 148984
2012-01-25 21:53:23 +00:00
82f76d1275
ARM assemly parsing and validation of IT instruction.
...
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
llvm-svn: 148969
2012-01-25 19:52:01 +00:00
0e496cddf0
Use precomputed BB size instead of BB->size().
...
llvm-svn: 148964
2012-01-25 18:54:13 +00:00
33633a90a0
fix a bug I introduced in r148929, this is not a splat!
...
Thanks to Eli for noticing.
llvm-svn: 148947
2012-01-25 09:56:22 +00:00
3c3feaf40c
Gracefully degrade precision in branch probability numbers.
...
llvm-svn: 148946
2012-01-25 09:43:14 +00:00
70d50ee8fb
Support pointer comparisons against constants, when looking at the inline-cost
...
savings from a pointer argument becoming an alloca. Sometimes callees will even
compare a pointer to null and then branch to an otherwise unreachable block!
Detect these cases and compute the number of saved instructions, instead of
bailing out and reporting no savings.
llvm-svn: 148941
2012-01-25 08:27:40 +00:00
6705883ad8
use Constant::getAggregateElement to simplify a bunch of code.
...
llvm-svn: 148934
2012-01-25 06:48:06 +00:00
7834900950
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
...
llvm-svn: 148933
2012-01-25 06:43:11 +00:00
7e683d10a8
constify some methods and add a new Constant::getAggregateElement
...
helper method for the common operation of extracting an element
out of a constant aggregate.
llvm-svn: 148931
2012-01-25 06:16:32 +00:00
47a86bdbe2
use ConstantVector::getSplat in a few places.
...
llvm-svn: 148929
2012-01-25 06:02:56 +00:00
ce4f9c5668
Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.
...
llvm-svn: 148927
2012-01-25 05:37:32 +00:00
e9eed29b5b
reapply r148901 with a crucial fix.
...
"Introduce a new ConstantVector::getSplat constructor function to
simplify a really common case."
llvm-svn: 148924
2012-01-25 05:19:54 +00:00
5bcf070e68
Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago.
...
llvm-svn: 148922
2012-01-25 04:42:03 +00:00
012f041bce
Mark 64-bit register RA_64 unused too.
...
llvm-svn: 148918
2012-01-25 04:19:22 +00:00
01d3c42f90
Modify MipsFrameLowering::emitPrologue and emitEpilogue.
...
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
instructions which store callee-saved registers have been emitted.
llvm-svn: 148917
2012-01-25 04:12:04 +00:00
d1d4b3efcf
Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to
...
expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.
llvm-svn: 148916
2012-01-25 03:55:10 +00:00
3ad5bc019a
Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions.
...
llvm-svn: 148914
2012-01-25 03:52:09 +00:00
6c421ea484
MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc.
...
inttypes.h is not supplied in msvc.
llvm-svn: 148912
2012-01-25 03:34:41 +00:00
ff50962534
Fix assert("msg"). Fix unused-variable warnings complaining about VT used only
...
in asserts.
llvm-svn: 148910
2012-01-25 03:20:12 +00:00
96a21dcea3
Target/Mips: Unbreak CMake build.
...
llvm-svn: 148909
2012-01-25 03:15:46 +00:00
86d5fadd57
Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added.
...
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.
llvm-svn: 148908
2012-01-25 03:01:35 +00:00
939b7a0b7c
Revert r148901 because it crashes llvm tests.
...
Original log:
Introduce a new ConstantVector::getSplat constructor function to
simplify a really common case.
llvm-svn: 148906
2012-01-25 02:42:41 +00:00
9fe7dd872b
Introduce a new ConstantVector::getSplat constructor function to
...
simplify a really common case.
llvm-svn: 148901
2012-01-25 01:53:58 +00:00
ff36fd3de3
Add class MipsAnalyzeImmediate which comes up with an instruction sequence to
...
load an immediate.
llvm-svn: 148900
2012-01-25 01:43:36 +00:00
8a3df5495a
Remove the Type::getNumElements() method, which is only called in 4 places,
...
did something extremely surprising, and shadowed actually useful
implementations that had completely different behavior.
llvm-svn: 148898
2012-01-25 01:32:59 +00:00
9be59599b3
Use the right method to get the # elements in a CDS.
...
llvm-svn: 148897
2012-01-25 01:27:20 +00:00
086cbfac7d
NEON VLD4(all lanes) assembly parsing and encoding.
...
llvm-svn: 148884
2012-01-25 00:01:08 +00:00
ccb6d55dae
Tidy up. Rename VLD4DUP patterns for consistency.
...
llvm-svn: 148883
2012-01-24 23:47:07 +00:00
b78403ce48
NEON VLD3(all lanes) assembly parsing and encoding.
...
llvm-svn: 148882
2012-01-24 23:47:04 +00:00
1b8e437ab6
Set correct <def,undef> flags when lowering REG_SEQUENCE.
...
A REG_SEQUENCE instruction is lowered into a sequence of partial defs:
%vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0
%vreg7:ssub_1<def> = COPY %vreg2
%vreg7:ssub_2<def> = COPY %vreg2
%vreg7:ssub_3<def> = COPY %vreg2
The first def needs an <undef> flag to indicate it is the beginning of
the live range, while the other defs are read-modify-write. Previously,
we depended on LiveIntervalAnalysis to notice and fix the missing
<def,undef>, but that solution was never robust, it was causing problems
with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE
instructions.
This fixes PR11841.
llvm-svn: 148879
2012-01-24 23:28:42 +00:00
66ef9ad33f
Use the standard MachineFunction::print() after SlotIndexes.
...
llvm-svn: 148878
2012-01-24 23:28:38 +00:00
d7970f9e4b
Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,
...
which is what N32/64 does.
llvm-svn: 148875
2012-01-24 23:18:43 +00:00
7e6c195c11
Pass CCState by reference.
...
llvm-svn: 148871
2012-01-24 22:07:36 +00:00
77dbd786c8
Pattern for f32 to i64 conversion.
...
llvm-svn: 148869
2012-01-24 22:05:25 +00:00
35bc8f9159
ARM Darwin symbol ref differences w/o subsection-via-symbols.
...
When not using subsections via symbols, the assembler can resolve
symbol differences (including pcrel references) to non-local
labels at assembly time, not just those in the same atom.
llvm-svn: 148865
2012-01-24 21:45:25 +00:00
a410ed3ced
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
...
llvm-svn: 148864
2012-01-24 21:43:36 +00:00
9f7ec1538f
64-bit sign extension in register instructions.
...
llvm-svn: 148862
2012-01-24 21:41:09 +00:00
88297ef665
Sink assert-only variables into the asserts
...
llvm-svn: 148849
2012-01-24 19:43:30 +00:00
c11d1dd133
[asan] enable asan only for the functions that have Attribute::AddressSafety
...
llvm-svn: 148846
2012-01-24 19:34:43 +00:00
8e2722cdb0
NEON VST4(one lane) assembly parsing and encoding.
...
llvm-svn: 148836
2012-01-24 18:53:13 +00:00
d845d9d9e9
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
...
llvm-svn: 148833
2012-01-24 18:37:29 +00:00
14952a0e32
NEON VLD4(one lane) assembly parsing and encoding.
...
llvm-svn: 148832
2012-01-24 18:37:25 +00:00
5b9deabae8
Fix old doxygen comment.
...
llvm-svn: 148825
2012-01-24 18:09:18 +00:00
3cfef8d467
NEON Two-operand assembly aliases for VSRA.
...
llvm-svn: 148821
2012-01-24 17:55:36 +00:00
7ae12cc546
NEON Two-operand assembly aliases for VSLI.
...
llvm-svn: 148819
2012-01-24 17:49:15 +00:00
7b6f0f67aa
NEON Two-operand assembly aliases for VSRI.
...
llvm-svn: 148818
2012-01-24 17:46:58 +00:00
681db34eae
NEON add correct predicates for some asm aliases.
...
llvm-svn: 148815
2012-01-24 17:23:29 +00:00
a0d01ff567
basic instcombine support for CDS.
...
llvm-svn: 148806
2012-01-24 14:31:22 +00:00
139822fc83
C++, CBE, and TLOF support for ConstantDataSequential
...
llvm-svn: 148805
2012-01-24 14:17:05 +00:00
2068393140
Rearrange argument order of ::get methods so that LLVMContext comes first,
...
add a ConstantDataArray::getString method that corresponds to the (to be
removed) StringRef version of ConstantArray::get, but is dramatically more
efficient.
llvm-svn: 148804
2012-01-24 14:04:40 +00:00
0b0c5d8c4c
ZERO_EXTEND operation is optimized for AVX.
...
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.
llvm-svn: 148803
2012-01-24 13:54:13 +00:00
00245f420a
add more support for ConstantDataSequential
...
llvm-svn: 148802
2012-01-24 13:41:11 +00:00
33a7e2f2a1
An option to selectively enable part of ARM EHABI support.
...
This change adds an new option --arm-enable-ehabi-descriptors that
enables emitting unwinding descriptors. This provides a mode with a
working backtrace() without the (currently broken) exception support.
llvm-svn: 148800
2012-01-24 13:05:33 +00:00
8aefffca4c
Bit pack DIE structures better.
...
16 bits are sufficient to store attributes, tags and forms.
llvm-svn: 148799
2012-01-24 12:08:28 +00:00
3e8ccc2000
Remove generation of DW_AT_sibling. Nothing as far as I can tell uses it.
...
Saves about 1.5% on debug info size.
rdar://10278198
llvm-svn: 148794
2012-01-24 09:43:28 +00:00
5d4497bf4a
Add AsmPrinter (aka MCLowering) support for ConstantDataSequential,
...
and clean up some other misc stuff. Unlike ConstantArray, we will
prefer to emit .fill directives for "String" arrays that all have
the same value, since they are denser than emitting a .ascii
llvm-svn: 148793
2012-01-24 09:31:43 +00:00
5dd4d87ce0
Add various "string" methods to ConstantDataSequential, which have the
...
same semantics as ConstantArray's but much more efficient because they
don't have to return std::string's. The ConstantArray methods will
eventually be removed.
llvm-svn: 148792
2012-01-24 09:01:07 +00:00
f7eb543380
teach valuetracking about ConstantDataSequential
...
llvm-svn: 148790
2012-01-24 07:54:10 +00:00
e166a8548f
switch SCEV to use the new ConstantFoldLoadThroughGEPIndices function
...
instead of its own hard coded thing, allowing it to handle
ConstantDataSequential and fixing some obscure bugs (e.g. it would
previously crash on a CAZ of vector type).
llvm-svn: 148788
2012-01-24 05:49:24 +00:00
f488b35826
Split the interesting bits of ConstantFoldLoadThroughGEPConstantExpr
...
out into a new ConstantFoldLoadThroughGEPIndices (more useful) function
and rewrite it to be simpler, more efficient, and to handle the new
ConstantDataSequential type.
Enhance ConstantFoldLoadFromConstPtr to handle ConstantDataSequential.
llvm-svn: 148786
2012-01-24 05:43:50 +00:00
030af79b14
Add some accessor methods to CAZ and UndefValue that help simplify clients.
...
Make some CDS methods public.
llvm-svn: 148785
2012-01-24 05:42:11 +00:00
3cad0c21ed
Use correct register class for am2offset register operands.
...
This pacifies machine verifier
llvm-svn: 148782
2012-01-24 04:58:56 +00:00
c46534a0cd
Preserve <def,undef> flags in CoalesceExtSubRegs.
...
This won't have an effect until EliminateRegSequences() starts setting
the undef flags.
llvm-svn: 148779
2012-01-24 04:44:01 +00:00
e4f3f102c2
implement the ConstantDataSequential accessor methods.
...
No need for 'getOperand' :)
llvm-svn: 148778
2012-01-24 04:43:41 +00:00
0d8e67aebd
Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types.
...
llvm-svn: 148771
2012-01-24 03:03:17 +00:00
da70eac268
NEON VST4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148764
2012-01-24 00:58:13 +00:00
ed561fc850
NEON VLD4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148762
2012-01-24 00:43:17 +00:00
1e946a4f91
Tidy up. Remove some vertical space for readability.
...
llvm-svn: 148761
2012-01-24 00:43:12 +00:00
ed975232bc
Revert r148686 (and r148694, a fix to it) due to a serious layering
...
violation -- MC cannot depend on CodeGen.
Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.
Fixing this is likely going to require some non-trivial refactoring.
llvm-svn: 148759
2012-01-24 00:30:17 +00:00
17bacab475
Fix typo.
...
llvm-svn: 148757
2012-01-24 00:12:39 +00:00
d3d36d9315
NEON VST3(single element from one lane) assembly parsing.
...
llvm-svn: 148755
2012-01-24 00:07:41 +00:00
eba7d3dba9
Fix typo.
...
llvm-svn: 148751
2012-01-23 23:56:33 +00:00
1a74724fc9
NEON VST3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148748
2012-01-23 23:45:44 +00:00
ac2af3ffab
NEON VLD3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148745
2012-01-23 23:20:46 +00:00
820417af07
Add missed mayStore flag to STREXD / t2STREXD
...
llvm-svn: 148742
2012-01-23 22:57:52 +00:00
3756b91313
start the implementation of a new ConstantDataVector and ConstantDataArray
...
classes, per PR1324. Not all of their helper functions are implemented,
nothing creates them, and the rest of the compiler doesn't handle them yet.
llvm-svn: 148741
2012-01-23 22:57:10 +00:00
11eeeff24f
Remove extraneous ';'s.
...
llvm-svn: 148740
2012-01-23 22:55:02 +00:00
d3303ded75
Remove dead default.
...
llvm-svn: 148738
2012-01-23 22:37:11 +00:00
cf893a437e
Intel syntax: Robustify parsing of memory operand's displacement experssion.
...
llvm-svn: 148737
2012-01-23 22:35:25 +00:00
a8b444b08b
NEON VLD3 lane-indexed assembly parsing and encoding.
...
llvm-svn: 148734
2012-01-23 21:53:26 +00:00
3c47e37387
Add support for .cfi_signal_frame. Fixes pr11762.
...
llvm-svn: 148733
2012-01-23 21:51:52 +00:00
2f6377cafe
copyImplicitOps is redundant here - the loop above already copies these ops.
...
llvm-svn: 148725
2012-01-23 21:15:01 +00:00
20948fab69
Fix PR11829. PostRA LICM was too aggressive.
...
This fixes a typo in r148589.
llvm-svn: 148724
2012-01-23 21:01:15 +00:00
9082353e3b
Simplify debug output.
...
llvm-svn: 148723
2012-01-23 21:01:11 +00:00
e660fdd953
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
...
llvm-svn: 148721
2012-01-23 20:20:06 +00:00
d28ef9ac46
Simplify some NEON assembly pseudo definitions.
...
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
llvm-svn: 148718
2012-01-23 19:39:08 +00:00
54db64e2e4
Silence warnings in -asserts build
...
llvm-svn: 148715
2012-01-23 18:46:04 +00:00
880bc1644b
Intel syntax: Parse segment registers.
...
llvm-svn: 148712
2012-01-23 18:31:58 +00:00
c7f9fd4da8
convert CAZ, UndefValue, and CPN to use DenseMap's again, this time without
...
using OwningPtr. OwningPtr would barf when the densemap had to reallocate,
which doesn't appear to happen on the regression test suite, but obviously
happens in real life :)
llvm-svn: 148700
2012-01-23 15:20:12 +00:00
962c272f95
revert r148691 and 148693
...
llvm-svn: 148698
2012-01-23 15:09:44 +00:00
c94cf8faf6
Implemented AddressSanitizer::getPassName()
...
llvm-svn: 148697
2012-01-23 11:22:43 +00:00
28ea8f523b
ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.
...
llvm-svn: 148694
2012-01-23 09:14:42 +00:00
4494e1ae25
switch UndefValue and ConstantPointerNull over to DenseMap's for uniquing.
...
llvm-svn: 148693
2012-01-23 08:52:32 +00:00
1910c9c3a0
Replace a use of ConstantUniqueMap for CAZ constants with a simple DenseMap.
...
Now that the type system rewrite has landed, there is no need for its
complexity and std::map'ness.
llvm-svn: 148691
2012-01-23 08:42:38 +00:00
edd1d0acfc
Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns.
...
llvm-svn: 148687
2012-01-23 08:18:28 +00:00
482cdc4ebd
An option to selectively enable parts of ARM EHABI support.
...
This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.
llvm-svn: 148686
2012-01-23 07:57:39 +00:00
6b90c5d03e
Update more places to use target specific nodes for vector shifts instead of intrinsics.
...
llvm-svn: 148685
2012-01-23 06:46:22 +00:00
5e80db4e4f
Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed.
...
llvm-svn: 148684
2012-01-23 06:16:53 +00:00
624e30894a
Avoid using an invalidated iterator.
...
llvm-svn: 148681
2012-01-23 05:07:16 +00:00
abf456e320
The iteration order over a std::set<Module*> depends on the addresses of the
...
modules. Avoid that to make the order the linker sees the modules deterministic.
llvm-svn: 148676
2012-01-23 03:41:53 +00:00
20c98df340
Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments.
...
llvm-svn: 148672
2012-01-23 00:06:44 +00:00
c31ceda7d9
Make Value::isDereferenceablePointer() handle unreachable code blocks. (This
...
returns false in the event the computation feeding into the pointer is
unreachable, which maybe ought to be true -- but this is at least consistent
with undef->isDereferenceablePointer().) Fixes PR11825!
llvm-svn: 148671
2012-01-23 00:05:17 +00:00
0b7ad76bd0
Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
...
llvm-svn: 148670
2012-01-22 23:36:02 +00:00
bd4884371b
Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
...
llvm-svn: 148667
2012-01-22 22:42:16 +00:00
e197d943f3
Use Attributes::None instead of 0 after r148553 change on Attributes from unsigned to their own class.
...
llvm-svn: 148665
2012-01-22 20:05:26 +00:00
094626414d
Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
...
llvm-svn: 148664
2012-01-22 19:15:14 +00:00
0251f20ad1
Add an option to disable buggy copy propagation pass
...
llvm-svn: 148662
2012-01-22 14:08:34 +00:00
5482b9f535
Add fused multiple+add instructions from VFPv4.
...
Patch by Ana Pazos!
llvm-svn: 148658
2012-01-22 12:07:33 +00:00
bff72ba77e
Remove trailing spaces
...
llvm-svn: 148654
2012-01-22 09:02:48 +00:00
c3c80f0986
Basic runtime dynamic loading capabilities added to ELFObjectFile, implemented
...
in a subclass named DyldELFObject. This class supports rebasing the object file
it represents by re-mapping section addresses to the actual memory addresses
the object was placed in. This is required for MC-JIT implementation on ELF with
debugging support.
Patch reviewed on llvm-commits.
Developed together with Ashok Thirumurthi and Andrew Kaylor.
llvm-svn: 148653
2012-01-22 09:01:03 +00:00
058d647adf
Split the lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h header to smaller logical headers.
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ELF and MachO implementations of RuntimeDyldImpl go into their own header files now.
Reviewed on llvm-commits
llvm-svn: 148652
2012-01-22 07:05:02 +00:00
a4ed5246d8
Make code a little less verbose.
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llvm-svn: 148651
2012-01-22 03:07:48 +00:00
cb3433cd58
Remove unused X86 ISD node type defines.
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llvm-svn: 148644
2012-01-22 01:15:56 +00:00
123adfa0f3
Move some vector shift patterns into their instruction definitions.
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llvm-svn: 148643
2012-01-22 00:41:20 +00:00
dcaa5fbd08
Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions.
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llvm-svn: 148641
2012-01-21 18:37:15 +00:00
5cff13a3fb
Remove unused variables.
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llvm-svn: 148635
2012-01-21 10:42:44 +00:00
39bc1e4d25
Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that.
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llvm-svn: 148632
2012-01-21 08:49:33 +00:00
64a2beca52
Fix an obvious typo.
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llvm-svn: 148622
2012-01-21 03:31:03 +00:00
8e3bb315d8
Handle register masks in LiveVariables.
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A register mask operand kills any live physreg that isn't preserved.
Unlike an implicit-def operand, the clobbered physregs are never live
afterwards.
This means LiveVariables has to track a much smaller number of live
physregs, and it should spend much less time in addRegisterDead().
llvm-svn: 148609
2012-01-21 00:58:53 +00:00
8c592f13e3
RuntimeDyld alignment adjustment from MachO file.
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The MachO file stores section alignment as log2(alignment-in-bytes). The
allocation routines want the raw alignment-in-bytes value, so adjust
for that.
llvm-svn: 148604
2012-01-21 00:21:53 +00:00
78dcaed8ca
Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
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llvm-svn: 148601
2012-01-21 00:07:56 +00:00
52ee45d64a
Delete an unused member variable.
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llvm-svn: 148594
2012-01-20 22:48:59 +00:00
1dc4a77a23
Fix inverted condition.
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llvm-svn: 148593
2012-01-20 22:44:03 +00:00
ce6a2ca8c8
Intel syntax: Robustify register parsing.
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llvm-svn: 148591
2012-01-20 22:32:05 +00:00
6b17ef58a1
Support register masks in MachineLICM.
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Only PostRA LICM is affected.
llvm-svn: 148589
2012-01-20 22:27:12 +00:00
58614f2f5a
Handle register masks in DeadMachineInstructionElim.
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Don't track live physregs that are clobbered by a register mask operand.
llvm-svn: 148588
2012-01-20 22:27:09 +00:00
46a9f016c5
More dead code removal (using -Wunreachable-code)
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llvm-svn: 148578
2012-01-20 21:51:11 +00:00
b9c822ab0b
Handle a corner case with IV chain collection with bailout instead of assert.
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Fixes PR11783: bad cast to AddRecExpr.
llvm-svn: 148572
2012-01-20 21:23:40 +00:00
d0930fff85
Intel syntax: Parse ... PTR [-8]
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llvm-svn: 148570
2012-01-20 21:21:01 +00:00
Bill Wendling