2a22c5deff
[AMDGPU] Switch to the new addr space mapping by default
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This requires corresponding clang change.
Differential Revision: https://reviews.llvm.org/D40955
llvm-svn: 324101
2018-02-02 16:07:16 +00:00
8728c5f2db
AMDGPU: Cleanup subtarget features
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Try to avoid mutually exclusive features. Don't use
a real default GPU, and use a fake "generic". The goal
is to make it easier to see which set of features are
incompatible between feature strings.
Most of the test changes are due to random scheduling changes
from not having a default fullspeed model.
llvm-svn: 310258
2017-08-07 14:58:04 +00:00
9aa45f047f
AMDGPU: Add macro fusion schedule DAG mutation
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Try to increase opportunities to shrink vcc uses.
llvm-svn: 307313
2017-07-06 20:57:05 +00:00
3dbeefa978
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
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Currently the default C calling convention functions are treated
the same as compute kernels. Make this explicit so the default
calling convention can be changed to a non-kernel.
Converted with perl -pi -e 's/define void/define amdgpu_kernel void/'
on the relevant test directories (and undoing in one place that actually
wanted a non-kernel).
llvm-svn: 298444
2017-03-21 21:39:51 +00:00
0a1a7b6b23
Revert "AMDGPU: Enable ConstrainCopy DAG mutation"
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This reverts commit r287146.
This breaks few conformance tests.
llvm-svn: 287233
2016-11-17 16:41:49 +00:00
3b36bb1d87
AMDGPU: Enable ConstrainCopy DAG mutation
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This fixes a probably unintended divergence from the default
scheduler behavior.
llvm-svn: 287146
2016-11-16 20:35:23 +00:00
0d23ebe888
AMDGPU/SI: Implement a custom MachineSchedStrategy
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Summary:
GCNSchedStrategy re-uses most of GenericScheduler, it's just uses
a different method to compute the excess and critical register
pressure limits.
It's not enabled by default, to enable it you need to pass -misched=gcn
to llc.
Shader DB stats:
32464 shaders in 17874 tests
Totals:
SGPRS: 1542846 -> 1643125 (6.50 %)
VGPRS: 1005595 -> 904653 (-10.04 %)
Spilled SGPRs: 29929 -> 27745 (-7.30 %)
Spilled VGPRs: 334 -> 352 (5.39 %)
Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread
Code Size: 36688188 -> 37034900 (0.95 %) bytes
LDS: 1913 -> 1913 (0.00 %) blocks
Max Waves: 254101 -> 265125 (4.34 %)
Wait states: 0 -> 0 (0.00 %)
Totals from affected shaders:
SGPRS: 1338220 -> 1438499 (7.49 %)
VGPRS: 886221 -> 785279 (-11.39 %)
Spilled SGPRs: 29869 -> 27685 (-7.31 %)
Spilled VGPRs: 334 -> 352 (5.39 %)
Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread
Code Size: 34315716 -> 34662428 (1.01 %) bytes
LDS: 1551 -> 1551 (0.00 %) blocks
Max Waves: 188127 -> 199151 (5.86 %)
Wait states: 0 -> 0 (0.00 %)
Reviewers: arsenm, mareko, nhaehnle, MatzeB, atrick
Subscribers: arsenm, kzhuravl, llvm-commits
Differential Revision: https://reviews.llvm.org/D23688
llvm-svn: 279995
2016-08-29 19:42:52 +00:00
1041a646a9
AMDGPU : Add V_SAD_U32 instruction pattern.
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Differential Revision: http://reviews.llvm.org/D23069
llvm-svn: 279629
2016-08-24 14:59:47 +00:00
Yaxun Liu