Commit Graph

1492 Commits

Author SHA1 Message Date
Akira Hatanaka beea8a34c3 [mips] Refactor SYNC and multiply/divide instructions.
llvm-svn: 170955
2012-12-21 23:17:36 +00:00
Akira Hatanaka 31ddec5887 [mips] Refactor BAL instructions.
llvm-svn: 170954
2012-12-21 23:15:59 +00:00
Akira Hatanaka d6b694f036 [mips] Fix encoding of BAL instruction. Also, fix assembler test case which
was not catching the error.

llvm-svn: 170953
2012-12-21 23:13:59 +00:00
Akira Hatanaka a158042a56 [mips] Refactor jump, jump register, jump-and-link and nop instructions.
llvm-svn: 170952
2012-12-21 23:03:50 +00:00
Akira Hatanaka e1826d7464 [mips] Refactor load/store left/right and load-link and store-conditional
instructions.

llvm-svn: 170950
2012-12-21 23:01:24 +00:00
Akira Hatanaka d9bf8424e5 [mips] Refactor load/store instructions.
llvm-svn: 170948
2012-12-21 22:58:55 +00:00
Akira Hatanaka b59b047fbe [mips] Remove unnecessary isPseudo parameter.
llvm-svn: 170947
2012-12-21 22:57:26 +00:00
Akira Hatanaka e738efc95b [mips] Refactor LUI instruction.
llvm-svn: 170944
2012-12-21 22:46:07 +00:00
Akira Hatanaka 895e1cb2aa [mips] Refactor count leading zero or one instructions.
llvm-svn: 170942
2012-12-21 22:43:58 +00:00
Akira Hatanaka 4f4c4aa05e [mips] Refactor sign-extension-in-register instructions.
llvm-svn: 170940
2012-12-21 22:41:52 +00:00
Akira Hatanaka b14c6e4e5f [mips] Refactor instructions which copy from and to HI/LO registers.
llvm-svn: 170939
2012-12-21 22:39:17 +00:00
Akira Hatanaka 9e89195dce [mips] Refactor logical NOR instructions.
llvm-svn: 170937
2012-12-21 22:35:47 +00:00
Akira Hatanaka ac10697207 [mips] Move instruction definitions in MipsInstrInfo.td.
llvm-svn: 170936
2012-12-21 22:33:43 +00:00
Reed Kotler 9bff1ead0e Call llvm_unreachable instead of assert.
llvm-svn: 170822
2012-12-21 00:44:59 +00:00
Reed Kotler d11acc7dc0 Implement cfi_def_cfa_offset. "Make check" test case for this comming in the
next few days but it's already tested a lot from test-suite and works fine.
This patch completes almost 100% pass of test-suite for mips 16.

llvm-svn: 170674
2012-12-20 06:59:37 +00:00
Reed Kotler 8965d24a2a There is one more patch to finish large frames. Make sure we assert
on code that has large frames which will not yet compile correctly.

llvm-svn: 170673
2012-12-20 06:57:00 +00:00
Reed Kotler 7bff8f1d7a set register class properly for mips16 here
llvm-svn: 170669
2012-12-20 06:06:35 +00:00
Reed Kotler 92fc33bc97 This assert is overly restrictive and does not work for mips16.
llvm-svn: 170667
2012-12-20 05:09:15 +00:00
Reed Kotler fd633229f7 Turn on register scavenger for Mips 16
We use an unused Mips 32 register for the emergency slot
instead of using the stack.

llvm-svn: 170665
2012-12-20 04:44:58 +00:00
Akira Hatanaka e7f1acc7c0 [mips] Refactor SLT (set on less than) instructions. Separate encoding
information from the rest. 

llvm-svn: 170664
2012-12-20 04:27:52 +00:00
Akira Hatanaka bbd197e9c4 [mips] Refactor unconditional branch instruction. Separate encoding information
from the rest. 

llvm-svn: 170663
2012-12-20 04:22:39 +00:00
Akira Hatanaka b1527b7505 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
parameter.

llvm-svn: 170661
2012-12-20 04:20:09 +00:00
Akira Hatanaka 14f9ce0f83 [mips] Delete definition of CPRESTORE instruction.
llvm-svn: 170660
2012-12-20 04:15:30 +00:00
Akira Hatanaka c0ea0bb99b [mips] Refactor conditional branch instructions with one register operand.
Separate encoding information from the rest.

llvm-svn: 170659
2012-12-20 04:13:23 +00:00
Akira Hatanaka f71ffd29d9 [mips] Refactor conditional branch instructions with two register operands.
Separate encoding information from the rest.

llvm-svn: 170657
2012-12-20 04:10:13 +00:00
Reed Kotler d019dbf75e fix most of remaining issues with large frames.
these patches are tested a lot by test-suite but
make check tests are forthcoming once the next
few patches that complete this are committed.
with the next few patches the pass rate for mips16 is
near 100%

llvm-svn: 170656
2012-12-20 04:07:42 +00:00
Akira Hatanaka f423672117 [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copy
physical register $r1 to $r0.

GNU disassembler recognizes an "or" instruction as a "move", and this change
makes the disassembled code easier to read.

Original patch by Reed Kotler.

llvm-svn: 170655
2012-12-20 04:06:06 +00:00
Akira Hatanaka 7d75f9e3d3 [mips] Change the order of template parameters. Move the default parameters to
the end. 

llvm-svn: 170651
2012-12-20 03:52:08 +00:00
Akira Hatanaka 244f9e874c [mips] Refactor shift instructions with register operands. Separate encoding
information from the rest.

llvm-svn: 170650
2012-12-20 03:48:24 +00:00
Akira Hatanaka 7f96ad325f [mips] Refactor shift immediate instructions. Separate encoding information
from the rest.

llvm-svn: 170649
2012-12-20 03:44:41 +00:00
Akira Hatanaka ab1b715bf2 [mips] Refactor arithmetic and logic instructions with immediate operands.
Separate encoding information from the rest.

llvm-svn: 170648
2012-12-20 03:40:03 +00:00
Akira Hatanaka 1b37c4af01 [mips] Refactor arithmetic and logic instructions. Separate encoding
information from the rest.

llvm-svn: 170647
2012-12-20 03:34:05 +00:00
Akira Hatanaka 73495897b1 [mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and
ArithLogicI as the instruction base classes.

llvm-svn: 170642
2012-12-20 03:00:16 +00:00
Roman Divacky e3d323052f Remove edis - the enhanced disassembler. Fixes PR14654.
llvm-svn: 170578
2012-12-19 19:55:47 +00:00
Reed Kotler 3aad762d1d Add some missing Defs and Uses.
llvm-svn: 170493
2012-12-19 04:06:15 +00:00
Reed Kotler aee4d5d194 This patch is needed to make c++ exceptions work for mips16.
Mips16 is really a processor decoding mode (ala thumb 1) and in the same
program, mips16 and mips32 functions can exist and can call each other.

If a jal type instruction encounters an address with the lower bit set, then
the processor switches to mips16 mode (if it is not already in it). If the
lower bit is not set, then it switches to mips32 mode.

The linker knows which functions are mips16 and which are mips32.
When relocation is performed on code labels, this lower order bit is
set if the code label is a mips16 code label.

In general this works just fine, however when creating exception handling
tables and dwarf, there are cases where you don't want this lower order
bit added in.

This has been traditionally distinguished in gas assembly source by using a
different syntax for the label.

lab1:      ; this will cause the lower order bit to be added
lab2=.     ; this will not cause the lower order bit to be added

In some cases, it does not matter because in dwarf and debug tables
the difference of two labels is used and in that case the lower order
bits subtract each other out.

To fix this, I have added to mcstreamer the notion of a debuglabel.
The default is for label and debug label to be the same. So calling
EmitLabel and EmitDebugLabel produce the same result.

For various reasons, there is only one set of labels that needs to be
modified for the mips exceptions to work. These are the "$eh_func_beginXXX" 
labels.

Mips overrides the debug label suffix from ":" to "=." .

This initial patch fixes exceptions. More changes most likely
will be needed to DwarfCFException to make all of this work
for actual debugging. These changes will be to emit debug labels in some
places where a simple label is emitted now.

Some historical discussion on this from gcc can be found at:
http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html
http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html 

llvm-svn: 170279
2012-12-16 04:00:45 +00:00
Reed Kotler 5fdeb21249 This code implements most of mips16 hardfloat as it is done by gcc.
In this case, essentially it is soft float with different library routines.
The next step will be to make this fully interoperational with mips32 floating
point and that requires creating stubs for functions with signatures that
contain floating point types.

I have a more sophisticated design for mips16 hardfloat which I hope to
implement at a later time that directly does floating point without the need
for function calls.

The mips16 encoding has no floating point instructions so one needs to
switch to mips32 mode to execute floating point instructions.

llvm-svn: 170259
2012-12-15 00:20:05 +00:00
Patrik Hagglund 5e6c361bc0 Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.

This is the first, in a series of patches.

This is the second attempt. In the first attempt (r169837), a few
getSimpleVT() were hoisted too far, detected by bootstrap failures.

llvm-svn: 170104
2012-12-13 06:34:11 +00:00
Akira Hatanaka cf9a61b6ee [mips] Do not copy GOT address to register $gp if the function being called has
internal linkage.

llvm-svn: 170092
2012-12-13 03:17:29 +00:00
Akira Hatanaka b2cc8a756f [mips] Delete all floating point instruction classes that are no longer used.
No functionality change.

llvm-svn: 170084
2012-12-13 02:05:02 +00:00
Akira Hatanaka 6262bbf819 [mips] Modify definitions of floating point conditional move instructions.
No functionality change.

llvm-svn: 170080
2012-12-13 01:41:15 +00:00
Akira Hatanaka 79e1cdb00b [mips] Modify definitions of floating point comparison instructions.
No functionality change.

llvm-svn: 170077
2012-12-13 01:34:09 +00:00
Akira Hatanaka fd9163b74c [mips] Modify definitions of floating point branch instructions.
No functionality change.

llvm-svn: 170076
2012-12-13 01:32:36 +00:00
Akira Hatanaka cd3dfd238e [mips] Modify definitions of floating point indexed load and store instructions.
No functionality change.

llvm-svn: 170075
2012-12-13 01:30:49 +00:00
Akira Hatanaka b0d4acbc65 [mips] Modify definitions of floating point multiply-add/sub instructions.
No functionality change.

llvm-svn: 170073
2012-12-13 01:27:48 +00:00
Akira Hatanaka 92994f4846 [mips] Modify definitions of floating point load and store instructions.
No functionality change.

llvm-svn: 170072
2012-12-13 01:24:00 +00:00
Akira Hatanaka 2b75dde5fa [mips] Modify definitions of move from/to coprocessor instructions.
No functionality change.

llvm-svn: 170071
2012-12-13 01:16:49 +00:00
Akira Hatanaka dea8f61ae0 [mips] Modify definitions of two register operand floating point instructions.
No functionality change.

llvm-svn: 170069
2012-12-13 01:14:07 +00:00
Akira Hatanaka 29b513871a [mips] Modify definitions of three register operand floating point instructions
and separate encoding information from the rest.

llvm-svn: 170066
2012-12-13 01:07:37 +00:00
Akira Hatanaka 84693d5606 [mips] Move classes that do not belong in MipsInstrFormats.td into
MipsInstrFPU.td.
 

llvm-svn: 170061
2012-12-13 00:49:23 +00:00