efd97044a3
Mark MOVZX16/MOVSX16 as neverHasSideEffects/mayLoad
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llvm-svn: 160953
2012-07-30 07:14:07 +00:00
c6b7ef61f4
Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.
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llvm-svn: 160951
2012-07-30 06:48:11 +00:00
6eb6528b98
Intel Atom instruction itineraries for mov sign extension and mov zero extension.
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Patch by Tyler Nowicki!
llvm-svn: 151743
2012-02-29 19:44:41 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
464fcc0035
Constrain both operands on MOVZX32_NOREXrr8.
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This instruction is explicitly encoded without an REX prefix, so both
operands but be *_NOREX.
Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX
constraints are not satisfied.
This fixes a miscompilation in 20040709-2 in the gcc test suite.
llvm-svn: 141410
2011-10-07 20:15:54 +00:00
91f1d24736
Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.
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rdar://problem/8614450
llvm-svn: 131746
2011-05-20 19:04:40 +00:00
c72240bbd9
Reverting 131641 to investigate 'bot complaint.
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llvm-svn: 131654
2011-05-19 17:54:42 +00:00
b476b0cc9f
Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be
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pseudos. rdar://problem/8614450
llvm-svn: 131641
2011-05-19 16:59:50 +00:00
178f4bb62d
make the asm matcher emitter reject instructions that have comments
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in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
llvm-svn: 117897
2010-11-01 04:44:29 +00:00
9492c17baf
two changes: make the asmmatcher generator ignore ARM pseudos properly,
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and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
llvm-svn: 117861
2010-10-31 19:15:18 +00:00
89497a990e
add new file
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llvm-svn: 115606
2010-10-05 06:52:35 +00:00
Craig Topper