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3 Commits

Author SHA1 Message Date
Eugene Leviant 8e32aebe80 RuntimeDyldELF: implement R_AARCH64_PREL64 reloc 
Differential revision: https://reviews.llvm.org/D28122

llvm-svn: 291558
 2017-01-10 11:05:30 +00:00
Eugene Leviant 74f27dc91b RuntimeDyldELF: add missing test cases for AArch64 
llvm-svn: 291438
 2017-01-09 11:47:33 +00:00
Yichao Yu 8f8cdd00da Fix R_AARCH64_MOVW_UABS_G3 relocation 
Summary: The relocation is missing mask so an address that has non-zero bits in 47:43 may overwrite the register number. (Frequently shows up as target register changed to `xzr`....)

Reviewers: t.p.northover, lhames

Subscribers: davide, aemerson, rengolin, llvm-commits

Differential Revision: https://reviews.llvm.org/D27609

llvm-svn: 289880
 2016-12-15 22:36:53 +00:00