3 Commits

Author	SHA1	Message	Date
Pushpinder Singh	e1a31f52cd	[AMDGPU] Control num waves per EU for implicit work-group size ... Summary: If amdgpu-flat-work-group-size is not specified in LLVM IR, the backend uses default value of 1024. For this, minimum waves per EU should be 4. However, backend is still setting minimum value to 1 instead of calculated value. This is not observed normally as frontend always provide amdgpu-flat-work-group-size attribute. Reviewers: rampitec, b-sumner, sameerds, msearles Reviewed By: rampitec Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D81991	2020-07-01 22:53:52 -04:00
Yaxun Liu	2a22c5deff	[AMDGPU] Switch to the new addr space mapping by default ... This requires corresponding clang change. Differential Revision: https://reviews.llvm.org/D40955 llvm-svn: 324101	2018-02-02 16:07:16 +00:00
Daniil Fukalov	2bfbadcbc1	[inlineasm] Fix crash when number of matched input constraint operands overflows signed char ... In a case when number of output constraint operands that has matched input operands doesn't fit to signed char, TargetLowering::ParseConstraints() can try to access ConstraintOperands (that is std::vector) with negative index. Reviewers: rampitec, arsenm Differential Review: https://reviews.llvm.org/D39125 llvm-svn: 316574	2017-10-25 12:51:32 +00:00