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278429 Commits

Author SHA1 Message Date
Simon Pilgrim af35b76bda Regenerate some scheduling tests that got missed 
llvm-svn: 320305
 2017-12-10 12:59:55 +00:00
Simon Pilgrim 320996576d [X86] Flag ZNVER1 scheduler model as complete 
We just have to locally tag COPY as WriteMove

llvm-svn: 320304
 2017-12-10 12:43:53 +00:00
Simon Pilgrim 8547645948 [X86] Flag SLM scheduler model as complete 
We just have to locally tag COPY as WriteMove

llvm-svn: 320303
 2017-12-10 12:36:29 +00:00
Simon Pilgrim 91c159d841 [X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classes 
llvm-svn: 320302
 2017-12-10 12:26:35 +00:00
Simon Pilgrim 6de94a1adc [X86] Tag SSE4A instructions as SSE INTALU scheduler classes 
llvm-svn: 320301
 2017-12-10 12:08:04 +00:00
Simon Pilgrim cd58171110 [X86] Flag BTVER2 scheduler model as complete 
We just have to locally tag COPY as WriteMove

llvm-svn: 320300
 2017-12-10 11:51:29 +00:00
Simon Pilgrim b7fb2e2fa1 [X86] Tag ADJSTACK instructions as INTALU scheduler class 
llvm-svn: 320299
 2017-12-10 11:34:08 +00:00
Dorit Nuzman 5809e70540 [SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCasts 
CreateAddRecFromPHIWithCastsImpl() adds an IncrementNUSW overflow predicate
which allows the PSCEV rewriter to rewrite this scev expression:
 (zext i8 {0, + , (trunc i32 step to i8)} to i32)
into
 {0, +, (sext i8 (trunc i32 step to i8) to i32)}

But then it adds the wrong Equal predicate:
 %step == (zext i8 (trunc i32 %step to i8) to i32).
instead of:
 %step == (sext i8 (trunc i32 %step to i8) to i32)

This is fixed here.

Differential Revision: https://reviews.llvm.org/D40641

llvm-svn: 320298
 2017-12-10 11:13:35 +00:00
Simon Pilgrim d038b475ac Fix MSVC 'not all control paths return a value' warning 
llvm-svn: 320297
 2017-12-10 11:05:14 +00:00
Simon Pilgrim 1a030016a6 [X86] Tag MORESTACK instructions as ret scheduler class 
llvm-svn: 320296
 2017-12-10 10:08:21 +00:00
Craig Topper 253562eb81 [X86] Fix duplicate entries in skylake server scheduler model by changing Z128 to Z256 
Based on the fact that the 'Y' version of the instruction is next to this, I assume Z256 is the intended value.

llvm-svn: 320295
 2017-12-10 09:14:45 +00:00
Craig Topper 90c9c15936 [X86] Add MOVQI2PQIrm, MOVSDmr, and MOVSDrm to scheduler information 
The VEX versions were present but not the legacy SSE versions.

llvm-svn: 320294
 2017-12-10 09:14:44 +00:00
Craig Topper 28e55386ac [X86] Add LEA64_32r to scheduler models for Sandybridge,Haswell,Broadwell,Skylake 
llvm-svn: 320293
 2017-12-10 09:14:42 +00:00
Craig Topper 8ade4640f3 [X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,Skylake 
Sandy Bridge is also missing it, but it has other issues. See PR35590.

llvm-svn: 320292
 2017-12-10 09:14:41 +00:00
Craig Topper 1a88c50fd7 [X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP. 
llvm-svn: 320291
 2017-12-10 09:14:39 +00:00
Craig Topper c89e282f7d [X86] Rename some instructions so that 'b' is added as a suffix instead of replacing an 'r' 
llvm-svn: 320290
 2017-12-10 09:14:38 +00:00
Craig Topper 6c65910160 [X86] Add CMPSDrr/rm to the scheduler models. 
Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing.

llvm-svn: 320289
 2017-12-10 09:14:37 +00:00
Craig Topper d435a1950f [Docs] Fix typo in scheduler model documentation. enumemation->enumeration 
llvm-svn: 320288
 2017-12-10 09:14:35 +00:00
Tim Northover cf4701bb89 PowerPC: support external pid instructions in MC layer. 
This adds assembly & disassembly support for the e500mc "external pid"
instructions.

See https://reviews.llvm.org/D39249.

Patch by vit9696 <vit9696@avp.su>

llvm-svn: 320287
 2017-12-10 08:43:19 +00:00
Tim Northover 8f1bc370e2 PPC32: Support R_PPC_PLTREL32 in static mode. 
See https://reviews.llvm.org/D39226

Patch by vit9696 <vit9696@avp.su>

llvm-svn: 320286
 2017-12-10 08:42:34 +00:00
Xinliang David Li fa3f1a15b2 [PGO] change arg type to uint64_t to match member field type 
llvm-svn: 320285
 2017-12-10 07:39:53 +00:00
Ahmed Bougacha 7008c6bc03 Update another sanitizer test for C++14. 
Follow-up to r320251.

llvm-svn: 320284
 2017-12-10 05:50:23 +00:00
Craig Topper da7e78e18c [X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since they can only be selected by intrinsics. 
llvm-svn: 320283
 2017-12-10 04:07:28 +00:00
Craig Topper 4e57776fb2 [X86] Correct the _Int part of more scheduler model instrexes. Put _b in the correct order relative to _Int 
llvm-svn: 320282
 2017-12-10 03:16:38 +00:00
Craig Topper a2f5528084 [X86] Remove ReadAfterLd from several several rb instructions 
This affects CVTSD2SS, FMA, RCP28, RSQRT28, and SQRT scalar instructions

'b' here refers to 'sae' not broadcast. These aren't memory instructions.

llvm-svn: 320281
 2017-12-10 03:16:36 +00:00
Craig Topper 29868dcbaa [X86] Fix test case I failed ot update in r320279. 
llvm-svn: 320280
 2017-12-10 01:27:54 +00:00
Craig Topper 391c6f9507 [X86] Fix bad regular expressions in the scheduler models. Question marks should be outside of multicharacter parenthesized expressions 
If the question mark is inside the parentheses it only applies to the single character proceeding it.

I had to make a few additional cleanups to fix some duplicate warnings that were exposed by fixing this.

llvm-svn: 320279
 2017-12-10 01:24:08 +00:00
Craig Topper 8ee98d0b51 [X86] Make the _Int part of some instregex sheduler patterns optional 
llvm-svn: 320278
 2017-12-10 01:24:06 +00:00
Craig Topper 5ffe80103e [X86] Add the commutable floating point min/max pseudo instructions to sandybridge,haswell,broadwell,skylakeclient scheduler models. 
llvm-svn: 320277
 2017-12-10 01:24:05 +00:00
Simon Pilgrim 6655eef1b4 [X86] Tag PIC setup instruction as jump scheduler class 
llvm-svn: 320276
 2017-12-10 00:40:37 +00:00
Simon Pilgrim 5d74949e5f [X86] Tag ACQUIRE/RELEASE atomic instructions as microcoded scheduler classes 
Note: We may be too pessimistic here and should possibly use something closer to the LOCK arithmetic instructions
llvm-svn: 320275
 2017-12-10 00:30:57 +00:00
Simon Pilgrim dcbe723d28 [X86] Tag TLS instructions as system scheduler classes 
llvm-svn: 320274
 2017-12-10 00:12:57 +00:00
Simon Pilgrim 3508a09455 [X86] Tag ALLOCA/VAARG instructions as system scheduler classes 
llvm-svn: 320273
 2017-12-10 00:03:16 +00:00
Joel Jones 5cc21e83ce [AArch64] Improve loop unrolling performance on Cavium T99 
This patch improves performance on Cavium T99 as shown here (libquantum 0.2.4):

https://docs.google.com/spreadsheets/d/1Lo1o2E1NjrpkwS7DvYYWsiVvPdd93h7KBaqeptMrZPY/edit?usp=sharing

By increasing the LoopMicroOpsBufferSize in the Cavium T99 Scheduler file,
loop unrolling becomes more aggressive. This helps performance on T99.

Test case included.

Patch by Stefan Teleman

Differential Revision: https://reviews.llvm.org/D40695 

llvm-svn: 320272
 2017-12-09 23:59:55 +00:00
Duncan P. N. Exon Smith 6c63b07a55 Update Clang CMake cache to use cxx-headers, NFC 
Apparently libcxx-headers is going away.  Fixes PR35584.

llvm-svn: 320271
 2017-12-09 23:44:42 +00:00
Simon Pilgrim a42a54258e [InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515) 
Don't assume that the pattern matched SRL can be cast to an Instruction (might be ConstExpr etc.)

llvm-svn: 320270
 2017-12-09 23:42:56 +00:00
Simon Dardis 70dbd5fbd0 Infer lowest bits of an integer Multiply when the low bits of the operands are known 
When the lowest bits of the operands to an integer multiply are known, the low bits of the result are deducible.
Code to deduce known-zero bottom bits already existed, but this change improves on that by deducing known-ones.

Patch by: Pedro Ferreira

Reviewers: craig.topper, sanjoy, efriedma

Differential Revision: https://reviews.llvm.org/D34029

llvm-svn: 320269
 2017-12-09 23:25:57 +00:00
Craig Topper f4e3044db9 [X86] Use KMOV instructions to zero upper bits of vectors when possible. 
llvm-svn: 320268
 2017-12-09 23:10:59 +00:00
Craig Topper 5ac75d5628 [X86] Improve lowering of vXi1 insert_subvectors to better utilize (insert_subvector zero, vec, 0) for zeroing upper bits. 
This can be better recognized during isel when the producer already zeroed the upper bits.

llvm-svn: 320267
 2017-12-09 22:44:42 +00:00
Simon Pilgrim e049038692 [X86] Tag LOCK/REX64/DATA16/DATA32 instruction prefix scheduler classes 
llvm-svn: 320266
 2017-12-09 21:27:03 +00:00
Simon Pilgrim b2b93f6204 Strip trailing whitespace. NFCI. 
llvm-svn: 320265
 2017-12-09 20:44:51 +00:00
Simon Pilgrim 7e636cc419 [X86] Tag FS/GS BASE R/W instruction scheduler classes 
llvm-svn: 320264
 2017-12-09 20:42:27 +00:00
Simon Pilgrim 231fab072f [X86] Tag REP/REPNE prefix instructions as microcoded scheduler classes 
llvm-svn: 320263
 2017-12-09 20:16:37 +00:00
Simon Pilgrim 2e7314eb2f [X86] Tag missing EH pseudo instruction scheduler classes 
llvm-svn: 320262
 2017-12-09 20:04:02 +00:00
Simon Pilgrim cb71e72707 [X86] Tag frame pointer XORs instruction scheduler classes 
llvm-svn: 320261
 2017-12-09 19:56:39 +00:00
Craig Topper 504534514c [X86] Don't use getTargetConstant for all 0s and all 1s mask vector. 
llvm-svn: 320260
 2017-12-09 19:18:30 +00:00
Kostya Serebryany de891a1946 [libFuzzer] even less aggressive step function for stack depth. Also don't use asan in one test to speed it up 
llvm-svn: 320259
 2017-12-09 19:18:10 +00:00
Adrian Prantl 844f8f21fd Remove duplicate option from documentation. 
llvm-svn: 320258
 2017-12-09 19:09:59 +00:00
Simon Pilgrim df702104d3 [X86] Tag segment prefixes as NOP instruction scheduling classes 
llvm-svn: 320257
 2017-12-09 16:58:34 +00:00
Rafael Espindola d26b52fd34 Remove some includes from InputFiles.h. 
They were not used in InputFiles.h and it was getting too easy to add
circular includes.

llvm-svn: 320256
 2017-12-09 16:56:18 +00:00