llvm-project

Commit Graph

Author	SHA1	Message	Date
Matt Arsenault	2e2af6026b	TableGen/GlobalISel: Emit enum names for reg class ID instead of value This was emitting the raw value for the reg class ID with a comment for the actual class name. Switch to emitting the qualified enum name instead, which obviates the need for the comment and also helps keep the lit tests on the emitter output more stable.	2020-07-13 14:02:08 -04:00
Matt Arsenault	cb5dc3765b	TableGen/GlobalISel: Fix constraining REG_SEQUENCE operands This was hitting the default instruction constraint code which uses the register classes in the instruction def, which REG_SEQUENCE does not have. Fixes not constraining the register class for AMDGPU fneg/fabs patterns, which would fail when the use was another generic, unconstrained instruction. Another oddity I noticed is that the temporary registers are created with an unnecessary, but incorrect 16-bit LLT but this shouldn't matter. I'm also still unclear why root and sub-instructions have to be handled differently.	2020-04-14 22:05:22 -04:00
Matt Arsenault	4a23ae5e78	GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542	2019-09-10 17:57:33 +00:00

Author

SHA1

Message

Date

Matt Arsenault

2e2af6026b

TableGen/GlobalISel: Emit enum names for reg class ID instead of value

This was emitting the raw value for the reg class ID with a comment
for the actual class name. Switch to emitting the qualified enum name
instead, which obviates the need for the comment and also helps keep
the lit tests on the emitter output more stable.

2020-07-13 14:02:08 -04:00

Matt Arsenault

cb5dc3765b

TableGen/GlobalISel: Fix constraining REG_SEQUENCE operands

This was hitting the default instruction constraint code which uses
the register classes in the instruction def, which REG_SEQUENCE does
not have.

Fixes not constraining the register class for AMDGPU fneg/fabs
patterns, which would fail when the use was another generic,
unconstrained instruction.

Another oddity I noticed is that the temporary registers are created
with an unnecessary, but incorrect 16-bit LLT but this shouldn't
matter.

I'm also still unclear why root and sub-instructions have to be
handled differently.

2020-04-14 22:05:22 -04:00

Matt Arsenault

4a23ae5e78

GlobalISel/TableGen: Handle REG_SEQUENCE patterns

The scalar f64 patterns don't work yet because they fail on multiple
results from the unused implicit def of scc in the result bit
operation.

llvm-svn: 371542

2019-09-10 17:57:33 +00:00

3 Commits