fed3d088ce
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
...
llvm-svn: 91313
2009-12-14 19:24:11 +00:00
20ac87de13
add Thumb2 atomic and memory barrier instruction definitions
...
llvm-svn: 91310
2009-12-14 18:56:47 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
...
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
f890f51666
80 column violations
...
llvm-svn: 89718
2009-11-24 00:20:27 +00:00
04c0e76772
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
...
llvm-svn: 89694
2009-11-23 20:35:53 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
...
llvm-svn: 89478
2009-11-20 19:57:15 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
...
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
b376ce0169
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
...
llvm-svn: 85965
2009-11-03 23:13:34 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
...
llvm-svn: 85824
2009-11-02 20:59:23 +00:00
5ac6f244fd
Fix schedule model for BFC.
...
llvm-svn: 85809
2009-11-02 17:28:36 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
...
llvm-svn: 85643
2009-10-31 03:39:36 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
...
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
b02bdb4552
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85184
2009-10-27 00:08:59 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
...
immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
423e42b371
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
...
llvm-svn: 84009
2009-10-13 18:59:48 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
...
ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
3bbc6c3ae6
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
...
llvm-svn: 83191
2009-10-01 01:33:39 +00:00
bcad0c8421
Add "isBarrier = 1" to return instructions.
...
Patch by Sylvere Teissier.
llvm-svn: 83135
2009-09-30 01:35:11 +00:00
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
...
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
7c2b1e71c1
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
...
This should be better than single load from constpool.
llvm-svn: 82948
2009-09-27 23:52:58 +00:00
a6b9cab822
Enable pre-regalloc load / store multiple pass for Thumb2.
...
llvm-svn: 82893
2009-09-27 09:46:04 +00:00
5f582b7290
RRX reads CPSR.
...
llvm-svn: 80699
2009-09-01 18:32:09 +00:00
4047b53a40
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
...
llvm-svn: 80350
2009-08-28 06:59:37 +00:00
ceffeb6abd
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
...
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
a7c2dfbca1
Update Cortex-A8 instruction itineraries for integer instructions.
...
llvm-svn: 79436
2009-08-19 18:00:44 +00:00
dd406177de
Fix revsh pattern.
...
llvm-svn: 79318
2009-08-18 05:43:23 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
...
llvm-svn: 78970
2009-08-14 00:32:16 +00:00
eba70d85cf
Add missing defs of R2 and D1.
...
llvm-svn: 78918
2009-08-13 16:59:44 +00:00
a9c2aad939
Finalize itineraries for cortex-a8 integer multiply
...
llvm-svn: 78908
2009-08-13 15:51:13 +00:00
695e1c6087
Remove unnecessary newline
...
llvm-svn: 78905
2009-08-13 15:12:16 +00:00
c96e88f8a5
Correct comment wording
...
llvm-svn: 78904
2009-08-13 15:11:43 +00:00
b369ee4c48
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
...
llvm-svn: 78827
2009-08-12 18:31:53 +00:00
a5fdfac6ca
register naming cleanup (s/ip/r12/)
...
llvm-svn: 78806
2009-08-12 15:21:13 +00:00
608d92c943
Remove an Darwin assembler workaround.
...
llvm-svn: 78777
2009-08-12 01:56:42 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
...
llvm-svn: 78717
2009-08-11 21:11:32 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
841850ed26
Add Thumb2 eh_sjlj_setjmp implementation
...
llvm-svn: 78701
2009-08-11 19:42:21 +00:00
d4d352c663
80 column violation.
...
llvm-svn: 78657
2009-08-11 08:47:46 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
51cbd2d6c4
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
...
llvm-svn: 78550
2009-08-10 02:37:24 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
...
'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
6e130db3b7
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
...
llvm-svn: 78410
2009-08-07 21:19:10 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
...
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
...
llvm-svn: 78321
2009-08-06 16:52:47 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
...
llvm-svn: 78126
2009-08-04 23:47:55 +00:00
03eb0e3c33
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
...
llvm-svn: 78030
2009-08-04 01:41:15 +00:00
e64f48ba8b
Workaround a couple of Darwin assembler bugs.
...
llvm-svn: 77781
2009-08-01 06:13:52 +00:00
e6e8289d72
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
...
llvm-svn: 77764
2009-08-01 01:43:45 +00:00
6ab54fdb0a
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
...
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
9eb3f88048
Thumb2 movcc need .w suffix.
...
llvm-svn: 77743
2009-07-31 22:21:55 +00:00
0bfc8312c2
Darwin assembler now recognizes "orn", so remove workaround.
...
llvm-svn: 77627
2009-07-30 21:51:41 +00:00
ce774e2383
Darwin assembler now supports "rrx", so remove workaround.
...
llvm-svn: 77625
2009-07-30 21:38:40 +00:00
cab137d294
Add missing D* register clobbers for Thumb-2 call.
...
llvm-svn: 77611
2009-07-30 18:01:09 +00:00
175bd14967
Make sure Thumb2 uses the right call instructions.
...
llvm-svn: 77507
2009-07-29 21:26:42 +00:00
0d98d8b8b3
- Fix an obvious copy and paste error.
...
- Darwin Thumb2 call clobbers r9.
llvm-svn: 77500
2009-07-29 20:10:36 +00:00
c6d70ae063
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
...
llvm-svn: 77422
2009-07-29 02:18:14 +00:00
c8bed03349
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
...
llvm-svn: 77364
2009-07-28 20:53:24 +00:00
68bb69d6e3
Remove support for ORN to workaround <rdar://problem/7096522>.
...
llvm-svn: 77363
2009-07-28 20:51:25 +00:00
865c6298d7
Add workaround for <rdar://problem/7098328>.
...
llvm-svn: 77340
2009-07-28 18:15:38 +00:00
e82862e24e
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
...
llvm-svn: 77329
2009-07-28 17:06:49 +00:00
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
...
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
57b51d9f82
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
...
llvm-svn: 77275
2009-07-27 23:34:12 +00:00
007031d1b4
Thumb-2 does not have RSC.
...
llvm-svn: 77201
2009-07-27 16:39:05 +00:00
782f242fd7
Add ".w" suffix for wide thumb-2 instructions.
...
llvm-svn: 77199
2009-07-27 16:31:55 +00:00
f3a1fce8ae
Change Thumb2 jumptable codegen to one that uses two level jumps:
...
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2 ]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
2009-07-25 00:33:29 +00:00
c64ce30c67
Uh. It would be useful to actually print the operand.
...
llvm-svn: 77004
2009-07-24 20:47:38 +00:00
666c912ce3
Make sure thumb2 jumptable entries are aligned.
...
llvm-svn: 76986
2009-07-24 18:20:44 +00:00
cdd405d804
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
...
llvm-svn: 76919
2009-07-24 00:16:18 +00:00
dc99f07113
Thumb2 does not allow the use of "pc" register as part of the load / store address.
...
llvm-svn: 76909
2009-07-23 23:09:51 +00:00
95a73e2eab
Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
...
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.
llvm-svn: 76889
2009-07-23 18:26:03 +00:00
6deba28c6f
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
...
llvm-svn: 76883
2009-07-23 17:06:46 +00:00
e270d4a4dd
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
...
llvm-svn: 76803
2009-07-22 22:03:29 +00:00
4b02b2f79c
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
...
llvm-svn: 76729
2009-07-22 06:46:53 +00:00
711b9e809c
CMP and TST define CPSR, not use it.
...
llvm-svn: 76489
2009-07-20 22:13:31 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
...
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
0f9cce7951
Add a thumb2 pass to insert IT blocks.
...
llvm-svn: 75218
2009-07-10 01:54:42 +00:00
1622d7b429
Fix ldm / stm unified syntax; add t2LDM_RET.
...
llvm-svn: 75188
2009-07-09 22:58:39 +00:00
7591d02c84
Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
...
Note, we are not yet generating these instructions.
llvm-svn: 75181
2009-07-09 22:21:59 +00:00
ad93707e16
Correct comment.
...
llvm-svn: 75172
2009-07-09 20:40:44 +00:00
22c2fba978
Use common code for both ARM and Thumb-2 instruction and register info.
...
llvm-svn: 75067
2009-07-08 23:10:31 +00:00
e3a53c448b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
...
llvm-svn: 75048
2009-07-08 21:03:57 +00:00
03ab0bbb24
Generalize opcode selection in ARMBaseRegisterInfo.
...
llvm-svn: 75036
2009-07-08 20:28:28 +00:00
af7451b674
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
...
llvm-svn: 75010
2009-07-08 16:09:28 +00:00
d0611f9a37
Add Thumb2 movcc instructions.
...
llvm-svn: 74946
2009-07-07 20:39:03 +00:00
d0f6324cdc
Add Thumb2 pkhbt / pkhtb.
...
llvm-svn: 74895
2009-07-07 05:35:52 +00:00
b24e51e2d9
Add some more Thumb2 multiplication instructions.
...
llvm-svn: 74889
2009-07-07 01:17:28 +00:00
40398233b7
Add bfc to armv6t2.
...
llvm-svn: 74868
2009-07-06 22:23:46 +00:00
0e8bde5910
Add thumb2 sign / zero extend with rotate instructions.
...
llvm-svn: 74755
2009-07-03 01:43:10 +00:00
6d9041100b
Add Thumb2 load / store multiple instructions. Not used yet.
...
llvm-svn: 74749
2009-07-03 00:18:36 +00:00
f30ee8820a
t2LDR_PRE etc are loads.
...
llvm-svn: 74741
2009-07-03 00:08:19 +00:00
53cdf022b6
Added indexed stores.
...
llvm-svn: 74740
2009-07-03 00:06:39 +00:00
8ecd7eb3f7
Sign extending pre/post indexed loads.
...
llvm-svn: 74736
2009-07-02 23:16:11 +00:00
84c6cda2ef
Thumb2 pre/post indexed loads.
...
llvm-svn: 74696
2009-07-02 07:28:31 +00:00
2c450d35ae
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
...
llvm-svn: 74692
2009-07-02 06:38:40 +00:00
86c7e20ca6
Add PIC load and store patterns for Thumb-2.
...
llvm-svn: 74577
2009-07-01 00:01:13 +00:00
a83100f687
Thumb-2 load and store double description. But nothing yet creates them.
...
llvm-svn: 74566
2009-06-30 22:50:01 +00:00
d0890a2bad
Add thumb-2 store word, halfword, and byte.
...
llvm-svn: 74555
2009-06-30 22:11:34 +00:00
28d6d87244
Improve Thumb-2 jump table support.
...
llvm-svn: 74549
2009-06-30 19:50:22 +00:00
27303cde82
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
...
llvm-svn: 74543
2009-06-30 18:04:13 +00:00
57726817aa
A few more load instructions.
...
llvm-svn: 74500
2009-06-30 02:15:48 +00:00
76b37950ca
Add Thumb-2 support for TEQ amd TST.
...
llvm-svn: 74468
2009-06-29 22:49:42 +00:00
dbf11ba800
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
...
llvm-svn: 74423
2009-06-29 15:33:01 +00:00
b23b50d54d
Implement Thumb2 ldr.
...
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
eab9ca7ea6
Renaming for consistency.
...
llvm-svn: 74368
2009-06-27 02:26:13 +00:00
5d8b6eef5a
Remove outdated comment.
...
llvm-svn: 74357
2009-06-26 23:39:02 +00:00
5285817490
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
...
llvm-svn: 74355
2009-06-26 23:13:13 +00:00
35ee722d42
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
...
llvm-svn: 74321
2009-06-26 20:45:56 +00:00
5960e6d974
ADC used to implement adde should use "adcs" opcode instead of "adc".
...
llvm-svn: 74293
2009-06-26 18:07:25 +00:00
0377f737ff
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
...
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
llvm-svn: 74288
2009-06-26 16:10:07 +00:00
5bf9011c2d
Mark a bunch of instructions commutable.
...
llvm-svn: 74237
2009-06-26 00:19:44 +00:00
97727a61f9
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
...
llvm-svn: 74228
2009-06-25 23:34:10 +00:00
16f357cccf
Use MVN for ~t2_so_imm immediates.
...
llvm-svn: 74223
2009-06-25 23:11:21 +00:00
c7ea8df67e
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
...
llvm-svn: 74200
2009-06-25 20:59:23 +00:00
d76f0be844
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
...
llvm-svn: 74158
2009-06-25 02:08:06 +00:00
6ea7ad0351
Add thumb2 add sp.
...
llvm-svn: 74156
2009-06-25 01:21:30 +00:00
83f979a48b
Add Thumb2 pc relative add.
...
llvm-svn: 74141
2009-06-24 23:47:58 +00:00
7d80d29187
Test instructions operands were printed in the wrong order.
...
llvm-svn: 73990
2009-06-23 19:56:37 +00:00
4983e4550e
Proper patterns for thumb2 shift and rotate instructions.
...
llvm-svn: 73987
2009-06-23 19:39:13 +00:00
e379107cdc
Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
...
llvm-svn: 73975
2009-06-23 18:14:38 +00:00
b45cebabc9
Obvious typo.
...
llvm-svn: 73967
2009-06-23 17:54:26 +00:00
431cf567de
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
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also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
llvm-svn: 73965
2009-06-23 17:48:47 +00:00
022a726a25
Replace isTwoAddress with operand constraint.
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llvm-svn: 73947
2009-06-23 05:23:49 +00:00
5658086052
Fix asm string from MOVi16
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llvm-svn: 73661
2009-06-17 23:43:36 +00:00
02bb33c58d
Initial support for some Thumb2 instructions.
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Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
llvm-svn: 73622
2009-06-17 18:13:58 +00:00
b6f4538683
Add placeholder for thumb2 stuff
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llvm-svn: 72593
2009-05-29 23:41:08 +00:00
Jim Grosbach